Atmel AT89C5132 AT89C5132

8

4173ES–USB–09/07

AT89C5132

Table 11. Keypad Interface Si gnal Description

Table 12. External Access Signal Description

Table 13. Syst em Signal Description

Signal

Name Type Description Alternate

Function

KIN3:0 I Keypad Input Lines

Holding one of these pins high or low for 24 oscillator periods triggers a

keypad interrupt. P1.3:0

Signal

Name Type Description Alternate

Function

A15:8 I/O Address Lines

Upper address lines for the external bus.

Multiplexed higher address and data lines for the IDE interface. P2.7:0

AD7:0 I/O Address/Data Lines

Multiplexed lower address and data lines for the external memory or the IDE

interface. P0.7:0

ALE O

Address Latch Enable Output

ALE signals the start of an external bus cycle and indicates that valid address

information is available on lines A7:0. An external latch is used to demultiplex

the address from address/data bus.

-

ISP I/O ISP Enable Input

This signal must be held to GND through a pull-down resistor at the falling

reset to force execution of the internal bootloader. -

RD ORead Signal

Read signal asserted during external data memory read operation. P3.7

WR OWrite Signal

Write signal asserted during external data memory write operation. P3.6

Signal

Name Type Description Alternate

Function

RST I

Reset Input

Holding this pin high for 64 oscillator periods while the oscillator is running

resets the device. The Port pins are driven to their reset conditions when a

voltage lower than VIL is applied, whether or not the oscillator is running.

This pin has an internal pull-down resistor which allows the device to be reset

by connecting a capacitor between this pin and VDD.

Asserting RST when the chip is in Idle mode or Power-Down mode returns the

chip to normal operation.

-

TST I Test I nput

Test mode entry signal. This pin must be set to VDD.-

Contents

Main Features 1. Description 2. Typical Applications USB Microcontroller with 64K Bytes Flash Memory AT89C5132 2 AT89C5132 3. Block Diagram Figure 3-1. AT89C5132 Block Diagram 3 AT89C5132 TQFP80 4. Pin Description Figure 4-1. AT89C5132 80-pin TQFP Package 4 4.1 Signals 5 AT89C5132 Table 3. Timer 0 and Timer 1 Signal Descri ption Table 2. Clock Signal Description 6 Table 4. Audio Interface Signal Descr iption Table 6. MutiMediaCard Interface Signal Desc ription Table 5. USB Controller Signal Desc ription 7 Table 7. UART Signal Description Table 10. A/D Conv erter Signal Description Table 8. SPI Controller Signal Desc ription Table 9. TWI Controller Signal Description AT89C5132 Table 11. Keypad Interface Si gnal Description Table 13. Syst em Signal Description Table 12. External Access Signal Description 9 AT89C5132 Table 14. Pow er Signal Description 10 4.2 Internal Pin Structure R Table 15. Detaile d Internal Pin Structure 5. Address Spaces Peripherals Clock Generator System Ports Timers/Counters Watchdog Timer AT89C5132 14 6. Electrical Characteristics 6.2.1 Digital Logic 6.1 Absolute Maximum Ratings 6.2 DC Characteristics Table 1. Digital DC Characteristics 15 6.2.2 IDD, IDL and IPD Test Conditions Figure 6-1. IDD Test Condition, Active Mode Table 1. Digital DC Characteristics 16 Figure 6-2. IDL Test Condition, Idle Mode Figure 6-3. IPD Test Condition, Power-Down Mode 6.2.3 A-to-D Converter Table 2. A-to-D Converter DC Characteristics Page Page 19 6.3 AC Characteristics 20 Table 8. External 8-bit Bus Cycle Data Write AC Timings 6.3.1.3 Waveforms Figure 6-8. External 8-bit Bus Cycle Data Read Waveforms Page 22 Table 11. External IDE 16-bit Bus Cycle Data Write AC Timings 23 6.3.2.3 Waveforms Figure 6-10. External IDE 16-bit Bus Cycle Data Read Waveforms Note: D15:8 is written in DAT16H SFR. Figure 6-11. External IDE 16-bit Bus Cycle Data Write Waveforms Note: D15:8 is the content of DAT16H SFR. 24 6.3.3.2 Timings Table 13. SPI Int erface Master AC Timing 25 6.3.3.3 Waveforms Figure 6-12. SPI Slave Waveforms (SSCPHA = 0) Note: 1. Not Defined but generally the LSB of the character which has just been received. Note: 1. Not Defined but generally the MSB of the character which has just been received. Figure 6-13. SPI Slave Waveforms (SSCPHA = 1) 26 Figure 6-14. SPI Master Waveforms (SSCPHA = 0) Note: 1. SS handled by software using general purpose port pin. Figure 6-15. SPI Master Waveforms (SSCPHA = 1) Note: 1. SS handled by software using general purpose port pin. 27 VDD = 2.7 to 3.3 V, TA = -40 to +85C 6.3.4.2 Waveforms Figure 6-16. Two Wire Wa veforms 28 6.3.5.3 Waveforms Figure 6-17. MMC Input Output Waveforms 29 Note: 32-bit format with Fs = 48 kHz. 6.3.6.3 Waveforms Figure 6-18. Audio Interface Waveforms 30 31 6.3.7.3 Waveforms Figure 6-19. Analog-to-Digital Converter Internal Waveforms Figure 6-20. Analog-to-Digital Converter Characteristics ADEN Bit ADSST Bit T T AT89C5132 33 6.3.9.2 Timings Table 22. Externa l Clock AC Timings VDD = 2.7 to 3.3V, TA= -40 to +85C 6.3.9.3 Waveforms Figure 6-23. External Clock Waveform Figure 6-24. AC Testing Input/Output Waveforms Figure 6-25. Float Waveforms 7. Ordering Information Possible Order Entries Page Page 9. Datasheet Revision History for AT89C5132 Atmel Corporation Atmel Operations Regional Headquarters Europe Asia Japan