Cypress CY2048WAF manual Features, Block Diagram, Die Pad Description

CY2048WAF

Flash Programmable Capacitor Tuning Array Die for Crystal Oscillator(XO)

Features Benefits

•Flash-programmable capacitor tuning array for low ppm initial frequency clock output

•Low clock output jitter

—4 ps typ. RMS period jitter

—±30 ps typ. peak-to-peak period jitter

•Flash-programmable dividers

•Two-pin programming interface

•On-chip oscillator runs from 10–48-MHz crystal

•Five selectable post-divide options, using reference oscillator output

•Programmable asynchronous or synchronous OE and PWR_DWN modes

•2.7V to 3.6V operation

•Controlled rise and fall times and output slew rate

•Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal

•Allows multiple programming opportunities to correct errors, and control excess inventory

•Enables programming of output frequency after packaging

•PPM clock output error can be adjusted in package

•Provides flexibility in output configurations and testing

•Enables low-power operation or output enable function

•Provides flexibility for system applications through selectable instantaneous or synchronous change in outputs

•Enables encapsulation in small-size, surface-mount packages

Block Diagram

PD#/OE

(SDATA/VPP)

CONFIGURATION

XIN

CRYSTAL

XOUT

OSCILLATOR

/ 1, 2, 4, 8, 16

OUT

(SCL)

VDD

VSS

Die Pad Description

H o rizo n tal S crib e

1

V D D

O U T

6

Notes:

X(max): 980 ∝m, Y(max): 988 ∝m

Y (m ax)

2

X O U T

Scribe: X = 70 ∝m, Y = 86 ∝m

V ertical

3

X IN

7 C 8 0 3 3 0 A

S crib e

Bond pad opening: 85 ∝m x 85 ∝m

Pad pitch: 175 ∝m (min.)

4 P D #/O E

V S S

5

d ie#/rev

Wafer thickness: 11 mils (Typ.)

X (m ax)

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA

95134

•

408-943-2600

Document #: 38-07738 Rev. *A

Revised December 12, 2005

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