Cypress manual CY62128B MoBL, Features, Functional Description1, Logic Block Diagram

CY62128B

MoBL®

1-Mbit (128K x 8) Static RAM

Features

•Temperature Ranges

—Commercial: 0°C to 70°C

—Industrial: –40°C to 85°C

—Automotive: –40°C to 125°C

•4.5V–5.5V operation

•CMOS for optimum speed/power

•Low active power

(70 ns, LL version, Commercial, Industrial)

—82.5 mW (max.) (15 mA)

•Low standby power

(70 ns, LL version, Commercial, Industrial)

—110 µW (max.) (15 µA)

•Automatic power-down when deselected

•TTL-compatible inputs and outputs

•Easy memory expansion with CE1, CE2, and OE options

Functional Description[1]

The CY62128B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected.

Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).

Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).

The CY62128B is available in a standard 450-mil-wide SOIC, 32-pin TSOP type I and STSOP packages.

Logic Block Diagram
		INPUT BUFFER		I/O 0
A0	ROW DECODER			I/O 1
A1				I/O 2
A2			SENSE AMPS
A3
A4		512x 256x 8		I/O 3
A5		ARRAY
A6				I/O 4
A7
A8				I/O 5
CE1		COLUMN	POWER	I/O 6
			DOWN
		DECODER
CE2				I/O 7
WE
OE		9 10 11 12 13 14 15 16
		A A A A A A A A
Note:

1.For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation	•	3901 North First Street	•	San Jose, CA 95134	•	408-943-2600
Document #: 38-05300 Rev. *C					Revised March 7, 2005

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