Cypress manual Switching Waveforms continued, Read Cycle No. 2 OE Controlled13, CY62128B MoBL

Models: CY62128B

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CY62128B

MoBL®

14.Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

15.Data I/O is high impedance if OE = VIH.

16.If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.

Document #: 38-05300 Rev. *C

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Contents

CMOS for optimum speed/power Low active power FeaturesLogic Block Diagram Low standby power 70 ns, LL version, Commercial, IndustrialProduct Portfolio Pin ConfigurationsPower Dissipation Pin DefinitionsOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings RangeAC Test Loads and Waveforms Thermal Resistance6Capacitance6 Data Retention Waveform62128B-55 Switching Characteristics7 Over the Operating RangeSwitching Waveforms 62128B-70Write Cycle No. 1 CE1 or CE2 Controlled15 Switching Waveforms continuedRead Cycle No. 2 OE Controlled13 CY62128B MoBLSwitching Waveforms continued Write Cycle No. 2 WE Controlled, OE HIGH During Write15Write Cycle No.3 WE Controlled, OE LOW15 CY62128B MoBLMoBL PowerCY62128B Truth Table32-Lead Thin Small Outline Package Type I 8x20 mm Z32 Package Diagrams32-Lead 450 MIL Molded SOIC S34 CY62128B MoBL32-Lead Reverse Thin Small Outline Package ZR32 Package Diagrams continued32-Lead Shrunk Thin Small Outline Package 8x13.4 mm ZA32 CY62128B MoBLDocument Title CY62128B MoBL 1-Mbit 128K x 8 Static RAM IssueDocument History Page Document Number