Cypress CY62128E manual Thermal Resistance9, AC Test Loads and Waveform, Data Retention Waveform11

MoBL® CY62128E

Thermal Resistance[9]

Parameter	Description	Test Conditions	SOIC	STSOP	TSOP	Unit
			Package	Package	Package
ΘJA	Thermal Resistance	Still Air, soldered on a 3 × 4.5 inch,	48.67	32.56	33.01	°C/W
	(Junction to Ambient)	two-layer printed circuit board
ΘJC	Thermal Resistance		25.86	3.59	3.42	°C/W
	(Junction to Case)

AC Test Loads and Waveform

R1

VCC

ALL INPUT PULSES

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

		3.0V			90%
R2	10%
		GND
	Rise Time = 1 V/ns
Equivalent to:	THEVENIN EQUIVALENT
OUTPUT			RTH	V

90%

10%

Fall Time = 1 V/ns

Parameters	Value	Unit
R1	1800	Ω
R2	990	Ω
RTH	639	Ω
VTH	1.77	V

Data Retention Characteristics (Over the Operating Range)

Parameter	Description				Conditions		Min		Typ[3]	Max	Unit
VDR	VCC for Data Retention							2			V
ICCDR [8]	Data Retention Current	VCC= VDR,		1	> VCC − 0.2V or CE2 < 0.2V,	Ind’l/Auto-A				4	μA
			CE
		VIN > VCC - 0.2V or VIN < 0.2V
						Auto-E				30	μ
											A
tCDR [9]	Chip Deselect to Data							0			ns
	Retention Time
t [10]	Operation Recovery						t	RC			ns
R	Time

Data Retention Waveform[11]

		VCC(min)	DATA RETENTION MODE		VCC(min)
V	CC		V	> 2.0V
		tCDR	DR		tR
CE

Notes

10.Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.

11.CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.

Document #: 38-05485 Rev. *F Page 4 of 12

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