MoBL® CY62128E
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Storage Temperature |
Output Current into Outputs (LOW) | ............................. 20 mA |
Static Discharge Voltage | > 2001V |
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Latch up Current | > 200 mA |
Ambient Temperature with |
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Power Applied | |||
Supply Voltage to Ground |
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Potential | |||
DC Voltage Applied to Outputs |
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in | CC(max) | + 0.5V) | |
DC Input Voltage[5, 6] |
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CC(max) | + 0.5V) | ||
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Electrical Characteristics (Over the Operating Range)
Operating Range
Device | Range | Ambient | [7] |
Temperature | VCC | ||
CY62128ELL | 4.5V to 5.5V | ||
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Parameter | Description |
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| Test Conditions | 45 ns |
| 55 ns | Unit | ||||||
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| Min | Typ[3] | Max | Min |
| Typ[3] | Max | ||||||
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VOH | Output HIGH |
| IOH = |
| 2.4 |
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| 2.4 |
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| V | ||
| Voltage |
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VOL | Output LOW |
| IOL = 2.1 mA |
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| 0.4 |
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| 0.4 | V | ||
| Voltage |
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VIH | Input HIGH Voltage | VCC = 4.5V to 5.5V | 2.2 |
| VCC + 0.5 | 2.2 |
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| VCC + 0.5 | V | ||||
VIL | Input LOW voltage |
| VCC = 4.5V to 5.5V |
| 0.8 |
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| 0.8 | V | |||||
IIX | Input Leakage |
| GND < VI < VCC |
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| +1 |
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| +4 | μA | ||||
| Current |
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IOZ | Output Leakage |
| GND < VO < VCC, Output Disabled |
| +1 |
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| +4 | μA | |||||
| Current |
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ICC | VCC Operating |
| f = fmax = 1/tRC |
| VCC = VCC(max) |
| 11 | 16 |
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| 11 | 35 | mA | |
| Supply Current |
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| IOUT = 0 mA |
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| f = 1 MHz |
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| 1.3 | 2 |
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| 1.3 | 4 |
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| CMOS levels |
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ISB2 [8] | Automatic CE |
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| 1 > VCC – 0.2V or CE2 < 0.2V, |
| 1 | 4 |
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| 1 | 30 | μA | ||
CE |
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| Power down |
| VIN > VCC – 0.2V or VIN < 0.2V, |
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| f = 0, VCC = VCC(max) |
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| Inputs |
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Capacitance (For all Packages) [9]
Parameter | Description | Test Conditions | Max | Unit |
CIN | Input Capacitance | TA = 25°C, f = 1 MHz, | 10 | pF |
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| VCC = VCC(typ) |
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COUT | Output Capacitance | 10 | pF |
Notes
5.VIL(min) =
6.VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
7.Full device AC operation assumes a 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.
8.Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
9.Tested initially and after any design or process changes that may affect these parameters.
Document #: | Page 3 of 12 |
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