CY14B101L
Document Number: 001-06400 Rev. *I Page 9 of 18
AC Switching Characteristics SRAM Read Cycle
Parameter Description 25 ns 35 ns 45 ns Unit
Min Max Min Max Min Max
Cypress
Parameter Alt
t
ACE
t
ELQV
Chip Enable Access Time 25 35 45 ns
t
RC [7]
t
AVAV,
t
ELEH
Read Cycle Time 25 35 45 ns
t
AA [8]
t
AVQV
Address Access Time 25 35 45 ns
t
DOE
t
GLQV
Output Enable to Data Valid 12 15 20 ns
t
OHA [8]
t
AXQX
Output Hold After Address Change 3 3 3 ns
t
LZCE [9]
t
ELQX
Chip Enable to Output Active 3 3 3 ns
t
HZCE [9]
t
EHQZ
Chip Disable to Output Inactive 10 13 15 ns
t
LZOE [9]
t
GLQX
Output Enable to Output Active 0 0 0 ns
t
HZOE [9]
t
GHQZ
Output Disable to Output Inactive 10 13 15 ns
t
PU [6]
t
ELICCH
Chip Enable to Power Active 0 0 0 ns
t
PD [6]
t
EHICCL
Chip Disable to Power Standby 25 35 45 ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled
[7, 8, 10]
Figure 6. SRAM Read Cycle 2: CE and OE Controlled
[7, 10]
W
5&
W
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W
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W
5&
&(
W
$&(
W
/=&(
W
3'
W
+=&(
2(
W
'2(
W
/=2(
W
+=2(
'$7$9$/,'
$&7,9(
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W
38
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,&&
Notes
7. WE and HSB must be HIGH during SRAM READ cycles.
8. Device is continuously selected with CE and OE both Low.
9. Measured ±200 mV from steady state output voltage.
10.HSB must remain high during READ and WRITE cycles.
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