Cypress CY14B101L manual Hardware Mode Selection A15 A0 Power

							CY14B101L
.
Table 1. Hardware Mode Selection
				A15 – A0	Mode	IO	Power
	CE	WE	OE
	H	X	X	X	Not Selected	Output High Z	Standby
	L	H	L	X	Read SRAM	Output Data	Active[3]
	L	L	X	X	Write SRAM	Input Data	Active
	L	H	L	0x4E38	Read SRAM	Output Data	Active[1, 2, 3]
				0xB1C7	Read SRAM	Output Data
				0x83E0	Read SRAM	Output Data
				0x7C1F	Read SRAM	Output Data
				0x703F	Read SRAM	Output Data
				0x8B45	AutoStore Disable	Output Data
	L	H	L	0x4E38	Read SRAM	Output Data	Active[1, 2, 3]
				0xB1C7	Read SRAM	Output Data
				0x83E0	Read SRAM	Output Data
				0x7C1F	Read SRAM	Output Data
				0x703F	Read SRAM	Output Data
				0x4B46	AutoStore Enable	Output Data
	L	H	L	0x4E38	Read SRAM	Output Data	Active ICC2[1, 2, 3]
				0xB1C7	Read SRAM	Output Data
				0x83E0	Read SRAM	Output Data
				0x7C1F	Read SRAM	Output Data
				0x703F	Read SRAM	Output Data
				0x8FC0	Nonvolatile Store	Output High Z
	L	H	L	0x4E38	Read SRAM	Output Data	Active[1, 2, 3]
				0xB1C7	Read SRAM	Output Data
				0x83E0	Read SRAM	Output Data
				0x7C1F	Read SRAM	Output Data
				0x703F	Read SRAM	Output Data
				0x4C63	Nonvolatile Recall	Output High Z

Notes

1.The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.

2.While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes.

3.IO state depends on the state of OE. The IO table shown is based on OE Low.

Document Number: 001-06400 Rev. *I Page 6 of 18

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