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| CY14B101L | ||
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SRAM Write Cycle |
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| Parameter |
| Description | 25 ns | 35 ns | 45 ns | Unit | ||||
Cypress |
| Alt |
| Min | Max | Min | Max | Min | Max | ||
Parameter |
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tWC |
| tAVAV |
| Write Cycle Time | 25 |
| 35 |
| 45 |
| ns |
tPWE |
| tWLWH, tWLEH |
| Write Pulse Width | 20 |
| 25 |
| 30 |
| ns |
tSCE |
| tELWH, tELEH |
| Chip Enable To End of Write | 20 |
| 25 |
| 30 |
| ns |
tSD |
| tDVWH, tDVEH |
| Data Setup to End of Write | 10 |
| 12 |
| 15 |
| ns |
tHD |
| tWHDX, tEHDX |
| Data Hold After End of Write | 0 |
| 0 |
| 0 |
| ns |
tAW |
| tAVWH, tAVEH |
| Address Setup to End of Write | 20 |
| 25 |
| 30 |
| ns |
tSA |
| tAVWL, tAVEL |
| Address Setup to Start of Write | 0 |
| 0 |
| 0 |
| ns |
tHA |
| tWHAX, tEHAX |
| Address Hold After End of Write | 0 |
| 0 |
| 0 |
| ns |
tHZWE [9,11] |
| tWLQZ |
| Write Enable to Output Disable |
| 10 |
| 13 |
| 15 | ns |
tLZWE [9] |
| tWHQX |
| Output Active After End of Write | 3 |
| 3 |
| 3 |
| ns |
Switching Waveforms
Figure 7. SRAM Write Cycle 1: WE Controlled [11, 12]
| tWC |
ADDRESS |
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| tSCE |
CE |
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| tAW |
| tSA |
WE | tPWE |
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| tSD |
DATA IN | DATA VALID |
| tHZWE |
| HIGH IMPEDANCE |
DATA OUT | PREVIOUS DATA |
tHA
tHD
tLZWE
Figure 8. SRAM Write Cycle 2: CE and OE Controlled [11, 12]
ADDRESS
CE
WE
DATA IN
DATA OUT
tWC
tSA |
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| tSCE |
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| tHA |
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tAW
tPWE
tSD tHD
DATA VALID
HIGH IMPEDANCE
Notes
11.If WE is Low when CE goes Low, the outputs remain in the high impedance state.
12.CE or WE must be greater than VIH during address transitions.
Document Number: | Page 10 of 18 |
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