Hardware Store Cycle

				CY14B101L

Hardware STORE Cycle

Parameter	Alt	Description	CY14B101L		Unit

			Min	Max
			Min	Max
tPHSB	tHLHX	Hardware STORE Pulse Width	15		ns
tDELAY [18]	tHLQZ , tBLQZ	Time Allowed to Complete SRAM Cycle	1	70	μs
t [19, 20]		Soft Sequence Processing Time		70	us
ss

Figure 12. Hardware STORE Cycle

3+6%

Notes

18.On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete.

19.This is the amount of time to take action on a soft sequence command. Vcc power must remain high to effectively register command.

20.Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.

Document Number: 001-06400 Rev. *I

Page 13 of 18

[+] Feedback

Image 13

Contents

Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation Pin Definitions Pinouts Sram Read Device OperationSram Write AutoStore Operation Low Average Active Power Hardware Recall Power UpSoftware Store Software Recall Best Practices Preventing Store Hardware Mode Selection A15 A0 Power Range Ambient Temperature DC Electrical CharacteristicsMaximum Ratings Operating Range Capacitance Data Retention and EnduranceThermal Resistance AC Test Conditions Switching Waveforms AC Switching CharacteristicsMin Max Parameter Data Setup to End of Write Chip Enable To End of WriteAddress Setup to End of Write Address Setup to Start of Write Parameter Alt Description CY14B101L Unit Min Max AutoStore or Power Up Recall Parameter Alt Description 25 ns 35 ns 45 ns Unit Min Max Software Controlled STORE/RECALL Cycle Parameter Alt Description CY14B101L Unit Min Hardware Store CycleHardware Store Pulse Width Ordering Information Part Numbering Nomenclature CY 14 B 101 L SZ 25 X C T Speed Ordering Code Package DiagramsPackage Type Operating Range Pin Shrunk Small Outline Package Document Title CY14B101L 1 Mbit 128K x 8 nvSRAM Document History USB Sales, Solutions, and Legal Information