Cypress CY62128E Switching Characteristics Over the Operating Range12, Read Cycle, Write Cycle15

									MoBL® CY62128E
Switching Characteristics (Over the Operating Range)[12]
Parameter					Description	45 ns (Ind’l/Auto-A)		55 ns (Auto-E)			Unit
						Min	Max	Min		Max
Read Cycle
tRC	Read Cycle Time					45		55			ns
tAA	Address to Data Valid						45			55	ns
tOHA	Data Hold from Address Change					10		10			ns
tACE		1 LOW and CE2 HIGH to Data Valid					45			55	ns
	CE
tDOE			LOW to Data Valid				22			25	ns
	OE
tLZOE			LOW to Low-Z[13]			5		5			ns
	OE
t			HIGH to High-Z[13, 14]				18				ns
	OE									20
HZOE
tLZCE		1 LOW and CE2 HIGH to Low-Z[13]				10		10			ns
	CE
t				HIGH or CE LOW to High-Z[13, 14]			18				ns
	CE	1								20
HZCE				2
tPU		1 LOW and CE2 HIGH to Power Up				0		0			ns
	CE
tPD		1 HIGH or CE2 LOW to Power Down					45			55	ns
	CE
Write Cycle[15]

tWC

tSCE

tAW

tHA

tSA

tPWE

tSD

tHD

tHZWE

tLZWE

Write Cycle Time			45		55		ns
	1 LOW and CE2 HIGH to Write End		35		40		ns
CE
Address Setup to Write End			35		40		ns
Address Hold from Write End			0		0		ns
Address Setup to Write Start			0		0		ns
		Pulse Width	35		40		ns
WE
Data Setup to Write End			25		25		ns
Data Hold from Write End			0		0		ns
		LOW to High-Z[13, 14]		18		20	ns
WE
		HIGH to Low-Z[13]	10		10		ns
WE

Notes

12.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the “” on page 4.

13.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

14.tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.

15.The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

Document #: 38-05485 Rev. *F Page 5 of 12

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