CY62138F MoBL®
2-Mbit (256K x 8) Static RAM
Features
•High speed: 45 ns
•Wide voltage range: 4.5 V – 5.5 V
•Pin compatible with CY62138V
•Ultra low standby power
—Typical standby current: 1 ∝A
—Maximum standby current: 5 ∝A
•Ultra low active power
—Typical active current: 1.6 mA @ f = 1 MHz
•Easy memory expansion with CE1, CE2, and OE features
•Automatic power down when deselected
•CMOS for optimum speed and power
•Available in
Logic Block Diagram
Functional Description [1]
The CY62138F is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL→) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A17).
To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and output enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins.
The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW).
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| A0 | DATA IN DRIVERS |
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| A1 |
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| IO |
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| A2 |
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| 1 |
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| DECODERROW |
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| AMPSSENSE |
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| A3 |
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| IO | ||
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| A4 |
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| 2 |
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| A5 |
| 256K x 8 |
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| IO | |||
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| A6 |
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| 3 |
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| A7 |
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| ARRAY |
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| A8 |
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| A9 |
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| IO |
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| A10 |
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| 5 |
CE1 |
| A11 |
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| IO6 |
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| IO7 | |
CE2 | WE |
| COLUMN DECODER | POWER | ||||||
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| DOWN |
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| OE |
| 12 | 13 | 14 | 15 | 16 | 17 |
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| A | A | A | A | A | A |
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Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation | • 198 Champion Court • San Jose, CA | • | |
Document #: | Revised March 26, 2007 | ||
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