Document #: 001-13194 Rev. *A Page 3 of 10
CY62138F MoBL®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential ................................–0.5V to 6.0V (VCCmax + 0.5V)
DC Voltage Applied to Outputs
in High-Z state [4, 5]................–0.5V to 6.0V (VCCmax + 0.5V)
DC Input Voltage [4, 5]............–0.5V to 6.0V (VCCmax + 0.5V)
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Device Range Ambient
Tempe ratu re VCC [6]
CY62138FLL Industrial –40°C to +85°C 4.5V to 5.5V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
45 ns
Unit
Min Typ [3] Max
VOH Output HIGH Voltage IOH = –1.0 mA 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage VCC = 4.5V to 5.5V 2.2 VCC + 0.5 V
VIL Input LOW Voltage VCC = 4.5V to 5.5V –0.5 0.8 V
IIX Input Leakage Current GND < VI < VCC –1 +1 µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA
ICC VCC Operating Supply
Current
f = fmax = 1/tRC VCC = VCC(max)
IOUT = 0 mA
CMOS levels
13 18 mA
f = 1 MHz 1.6 2.5
ISB2 [7] Automatic CE Power Down
Current CMOS inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max)
15µA
Capacitance (For all packages) [8]
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output capacitance 10 pF
Thermal Resistance [8]
Parameter Description Test Conditions SOIC TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch
two-layer printed circuit board
44.53 44.16 °C/W
ΘJC Thermal Resistance
(Junction to Case)
24.05 11.97 °C/W
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC+0.75V for pulse durations less than 20ns.
6. Full device AC operation assumes a 100 µs ramp time fr om 0 to VCC(min) and 200 µs wait time after VCC stabilization.
7. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
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