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CY62147EV30
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CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G
Page 11 of 13
Figure 13. 44-Pin TSOP II, 51-85087
Package Diagrams
(continued)
51-85087-*A
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Contents
Main
CY62147EV30 MoBL
4-Mbit (256K x 16) Static RAM
,
Features
Functional Description
Logic Block Diagram
CY62147EV30 MoBL
Pin Configuration
Figure 3. 44-Pin TSOP II
Figure 1. 48-Ball VFBGA (Single Chip Enable)
Figure 2. 48-Ball VFBGA (Dual Chip Enable)
CY62147EV30 MoBL
Maximum Ratings
Capacitance
Operating Range
Electrical Characteristics
CY62147EV30 MoBL
Thermal Resistance
Data Retention Characteristics
Switching Characteristics
CY62147EV30 MoBL
Figure 6. Read Cycle No. 1 (Address Transition Controlled)
PREVIOUS DATA VALID DATA VALID
Figure 7. Read Cycle No. 2 (OE Controlled)
ADDRESS DATA OUT
CY62147EV30 MoBL
Figure 8. Write Cycle No. 1 (WE Controlled)
Controlled)
Figure 9. Write Cycle No. 2 (CE
(continued)
Document #: 38-05440 Rev. *G Page 8 of 13
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW)
Figure 11. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
(continued)
Truth Table
Ordering Information
Package Diagrams
Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
51-85150-*D
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