CY62147EV30 MoBL
®
Document #: 38-05440 Rev. *G Page 2 of 13
Pin Configuration
Figure 1. 48-Ball VFBGA (Single Chip Enable)
[3, 4]
Figure 2. 48-Ball VFBGA (Dual Chip Enable)
[3, 4]
Figure 3. 44-Pin TSOP II
[3]
Product Portfolio
Product Range V
CC
Range (V) Speed
(ns)
Power Dissipation
Operating I
CC
(mA) Standby I
SB2
(μA)
f = 1 MHz f = f
max
Min Typ
[2]
Max Typ
[2]
Max Typ
[2]
Max Typ
[2]
Max
CY62147EV30LL Ind’l/Auto-A 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7
Auto-E 2.2 3.0 3.6 55 ns 2 3 15 25 1 20
WE
A
11
A
10
A
6
A
0
A
3
CE
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
A
7
IO
0
BHE
NC
A
2
A
1
BLE
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
NC
NC NC
326
5
41
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
A
17
WE
A
11
A
10
A
6
A
0
A
3
CE
1
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
A
7
IO
0
BHE
CE
2
A
2
A
1
BLE
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
NC
NC NC
326
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
A
17
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29
30
A
5
18
17
20
19 27
28
25
26
22
21 23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°.
3. NC pins are not connected on the die.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
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