CY62148BN MoBL®Document #: 001-06517 Rev. *A Page 4 of 10
Switching Characteristics[5] Over the Operating Range
Parameter Description
62148BNLL-70
UnitMin. Max.
READ CYCLE
tRC Read Cycle Time 70 ns
tAA Address to Data Valid 70 ns
tOHA Data Hold from Address Change 10 ns
tACE CE LOW to Data Valid 70 ns
tDOE OE LOW to Data Valid 35 ns
tLZOE OE LOW to Low Z[6] 5ns
tHZOE OE HIGH to High Z[6, 7] 25 ns
tLZCE CE LOW to Low Z[6] 10 ns
tHZCE CE HIGH to High Z[6, 7] 25 ns
tPU CE LOW to Power-Up 0ns
tPD CE HIGH to Power-Down 70 ns
WRITE CYCLE[8]
tWC Write Cycle Time 70 ns
tSCE CE LOW to Write End 60 ns
tAW Address Set-Up to Write End 60 ns
tHA Address Hold from Write End 0ns
tSA Address Set-Up to Write Start 0ns
tPWE WE Pulse Width 55 ns
tSD Data Set-Up to Write End 30 ns
tHD Data Hold from Write End 0ns
tLZWE WE HIGH to Low Z[6] 5ns
tHZWE WE LOW to High Z[6, 7] 25 ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, inp ut pulse l evels of 0 t o 3.0 V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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