Cypress CY62148BN Switching Characteristics5 Over the Operating Range, Read Cycle, Write Cycle

CY62148BN MoBL®

Switching Characteristics[5] Over the Operating Range

			62148BNLL-70
Parameter		Description			Unit
			Min.	Max.
READ CYCLE
tRC	Read Cycle Time		70		ns
tAA	Address to Data Valid			70	ns
tOHA	Data Hold from Address Change		10		ns
tACE		LOW to Data Valid		70	ns
	CE
tDOE		LOW to Data Valid		35	ns
	OE
tLZOE		LOW to Low Z[6]	5		ns
	OE
tHZOE		HIGH to High Z[6, 7]		25	ns
	OE
tLZCE		LOW to Low Z[6]	10		ns
	CE
tHZCE		HIGH to High Z[6, 7]		25	ns
	CE
tPU		LOW to Power-Up	0		ns
	CE
tPD		HIGH to Power-Down		70	ns
	CE
WRITE CYCLE[8]
tWC	Write Cycle Time		70		ns
tSCE		LOW to Write End	60		ns
	CE
tAW	Address Set-Up to Write End		60		ns
tHA	Address Hold from Write End		0		ns
tSA	Address Set-Up to Write Start		0		ns
tPWE		Pulse Width	55		ns
	WE
tSD	Data Set-Up to Write End		30		ns
tHD	Data Hold from Write End		0		ns
tLZWE		HIGH to Low Z[6]	5		ns
	WE
tHZWE		LOW to High Z[6, 7]		25	ns
	WE

Notes:

5.Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance.

6.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

7.tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

8.The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

Document #: 001-06517 Rev. *A Page 4 of 10

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