Cypress CY62148ESL Switching Characteristics, Parameter Read Cycle Description 55 ns Min Max Unit

CY62148ESL MoBL®

Switching Characteristics

Over the Operating Range [9]

Parameter

Read Cycle

Description

55 ns

Min Max

Unit

tRC	Read Cycle Time		55		ns
tAA	Address to Data Valid			55	ns
tOHA	Data Hold from Address Change		10		ns
tACE		LOW to Data Valid		55	ns
	CE
tDOE		LOW to Data Valid		25	ns
	OE
tLZOE		LOW to Low Z [10]	5		ns
	OE
tHZOE		HIGH to High Z [10, 11]		20	ns
	OE
tLZCE		LOW to Low Z [10]	10		ns
	CE
tHZCE		HIGH to High Z [10, 11]		20	ns
	CE
tPU		LOW to Power Up	0		ns
	CE
tPD		HIGH to Power Up		55	ns
	CE
Write Cycle [12]
tWC	Write Cycle Time		55		ns
tSCE		LOW to Write End	40		ns
	CE
tAW	Address Setup to Write End		40		ns
tHA	Address Hold from Write End		0		ns
tSA	Address Setup to Write Start		0		ns
tPWE		Pulse Width	40		ns
	WE
tSD	Data Setup to Write End		25		ns
tHD	Data Hold from Write End		0		ns
tHZWE		LOW to High Z [10, 11]		20	ns
	WE
tLZWE		HIGH to Low Z [10]	10		ns
	WE

Notes

9.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 4.

10.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

11.tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.

12.The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

Document #: 001-50045 Rev. ** Page 6 of 10

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