
CY62148ESL MoBL®
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [13, 14]
tRC
ADDRESS
tAA
tOHA
DATA OUT  | PREVIOUS DATA VALID  | 
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  | DATA VALID  | 
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  | Figure 4. Read Cycle No. 2 (OE Controlled) [14, 15] | 
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ADDRESS  | 
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  | tRC  | 
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CE  | 
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  | tACE  | 
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OE  | 
  | tHZOE  | 
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  | tDOE  | 
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  | tHZCE  | 
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  | tLZOE  | HIGH  | |
  | HIGH IMPEDANCE  | 
  | IMPEDANCE  | 
DATA OUT  | DATA VALID  | 
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tLZCE  | 
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  | |
  | tPD  | 
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V  | tPU  | ICC  | |
CC  | 50%  | 
  | 50%  | 
SUPPLY  | 
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CURRENT  | 
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  | ISB  | 
  | Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [16, 17] | 
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  | tWC  | 
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ADDRESS  | 
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  | tSCE  | 
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CE  | 
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  | tAW  | 
  | tHA  | 
  | tSA  | tPWE  | 
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WE  | 
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OE  | 
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  | tSD  | t  | 
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  | HD  | 
DATA IO | NOTE 18  | DATA VALID | 
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  | tHZOE  | 
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Notes
13.Device is continuously selected. OE, CE = VIL.
14.WE is HIGH for read cycles.
15.Address valid before or similar to CE transition LOW.
16.Data IO is high impedance if OE = VIH.
17.If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
18.During this period, the IOs are in output state. Do not apply input signals.
Document #:   | Page 7 of 10  | 
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