Cypress CY62148ESL

CY62148ESL MoBL

Document #: 001-50045 Rev. ** Page 9 of 10

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

55 CY62148ESL-55ZAXI 51-85094 32-Pin STSOP (Pb-Free) Industrial

Package Diagram

Figure 8. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094

51-85094-*D

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Contents

Main CY62148ESL MoBL , 4-Mbit (512K x 8) Static RAM Features Functional Description Logic Block Diagram CY62148ESL MoBL Pin Configuration Max Typ Typ SB2 Maximum Ratings Operating Range Electrical Characteristics CY62148ESL MoBL Capacitance Thermal Resistance Data Retention Characteristics Data Retention Waveform CY62148ESL MoBL Switching Characteristics Switching Waveforms Figure 3. Read Cycle No. 1 (Address Transition Controlled) Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) Figure 4. Read Cycle No. 2 (OE Controlled) CY62148ESL MoBL Switching Waveforms Figure 6. Write Cycle No. 2 (CE Controlled) Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) Truth Table Page Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions