Contents
Functional Description
Features
Logic Block Diagram
CY7B991 CY7B992
PLCC/LCC
Pin Configuration
Signal Name
Pin Definitions
Table 2. Programmable Skew Configurations1
Block Diagram Description
Phase Frequency Detector and Filter
where N =
CY7B991 CY7B992
Test Mode
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
Range
Maximum Ratings
Operating Range
Ambient
Parameter
Electrical Characteristics
CY7B991
CY7B992
TTL Input Test Waveform CY7B991
Capacitance
AC Test Loads and Waveforms
TTL AC Test Load CY7B991
Description
Switching Characteristics Over the Operating Range2
CY7B991 CY7B992
Parameter
CY7B991 CY7B992
CY7B991-5
CY7B992-5
Switching Characteristics
CY7B991 CY7B992
Switching Characteristics
CY7B991-7
CY7B992-7
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AC Timing Diagrams
CY7B991 CY7B992
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CY7B991 CY7B992
Figure 2. Zero Skew and Zero Delay Clock Driver
Operational Mode Descriptions
Figure 3. Programmable Skew Clock Driver
CY7B991 CY7B992
Figure 4. Inverted Output Connections
Figure 5. Frequency Multiplier with Skew Connectrions
Figure 6. Frequency Divider Connections
CY7B991 CY7B992
Figure 7. Multi-Function Clock Driver
Page 15 of
Figure 8. Board-to-Board Clock Distribution
CY7B991 CY7B992
Package Type
Ordering Information
Accuracy
Ordering Code
Group A Subgroup Testing
Military Specifications
DC Characteristics
Package Diagrams
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Package Diagrams continued
Figure 10. 32-Pin Rectangular Leadless Chip Carrier
CY7B991 CY7B992
Document Number
Issue Date
Document History
Document Title CY7B991/CY7B992 Programmable Skew Clock Buffer
