Cypress CY7C1020BN manual AC Test Loads and Waveforms, Write Cycle

CY7C1020BN

AC Test Loads and Waveforms

R 481Ω

5V

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE (a)

R 481Ω

5V

OUTPUT

R2	5 pF	R2
255Ω		255Ω

INCLUDING

JIG AND

SCOPE (b)

3.0V			ALL INPUT PULSES
		90%		90%
					10%
	10%
GND
Rise Time: 1 V/ns				Fall Time: 1 V/ns

167	Equivalent to: THÉVENIN OUTPUT		1.73V
	EQUIVALENT	30 pF

Switching Characteristics[5] Over the Operating Range

			7C1020BN-12		7C1020BN-15
Parameter		Description					Unit
			Min.	Max.	Min.	Max.
Read Cycle
tRC	Read Cycle Time		12		15		ns
tAA	Address to Data Valid			12		15	ns
tOHA	Data Hold from Address Change		3		3		ns
tACE		LOW to Data Valid		12		15	ns
	CE
tDOE		LOW to Data Valid		6		7	ns
	OE
tLZOE		LOW to Low Z[6]	0		0		ns
	OE
tHZOE		HIGH to High Z[6, 7]		6		7	ns
	OE
tLZCE		LOW to Low Z[6]	3		3		ns
	CE
tHZCE		HIGH to High Z[6, 7]		6		7	ns
	CE
tPU		LOW to Power-Up	0		0		ns
	CE
tPD		HIGH to Power-Down		12		15	ns
	CE
tDBE	Byte Enable to Data Valid			6		7	ns
tLZBE	Byte Enable to Low Z		0		0		ns
tHZBE	Byte Disable to High Z			6		7	ns
Write Cycle[8]
tWC	Write Cycle Time		12		15		ns
tSCE		LOW to Write End	9		10		ns
	CE
tAW	Address Set-Up to Write End		8		10		ns
tHA	Address Hold from Write End		0		0		ns
tSA	Address Set-Up to Write Start		0		0		ns
tPWE		Pulse Width	8		10		ns
	WE
tSD	Data Set-Up to Write End		6		8		ns
tHD	Data Hold from Write End		0		0		ns
tLZWE		HIGH to Low Z[6]	3		3		ns
	WE
tHZWE		LOW to High Z[6, 7]		6		7	ns
	WE
tBW	Byte Enable to End of Write		8		9		ns

Notes:

5.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.

6.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

7.tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

8.The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

Document #: 001-06443 Rev. ** Page 3 of 8

[+] Feedback