Cypress CY7C1041DV33 manual Read Cycle No. 2 OE Controlled 17, Write Cycle No. 1 CE Controlled19

CY7C1041DV33

Switching Waveforms (continued)
	Figure 5. Read Cycle No. 2 (OE Controlled)[17, 18]
ADDRESS
		tRC
CE
	tACE
OE		tHZOE
	tDOE
BHE, BLE
	tLZOE	tHZCE
	tDBE
	tLZBE	tHZBE
			HIGH
DATA OUT	HIGH IMPEDANCE	DATA VALID	IMPEDANCE
	tLZCE	tPD	IICC
VCC	tPU
SUPPLY	50%		50%
CURRENT			IISB

Figure 6. Write Cycle No. 1 (CE Controlled)[19, 20]

		tWC
ADDRESS
CE	tSA	tSCE
		tAW	tHA
		tPWE
WE
		tBW
BHE, BLE
		tSD	tHD
DATAIO

Notes

18.Address valid prior to or coincident with CE transition LOW.

19.Data IO is high impedance if OE or BHE and BLE = VIH.

20.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

Document #: 38-05473 Rev. *E Page 7 of 13

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