CY7C1041DV33
Data Retention Characteristics Over the Operating Range
Parameter | Description | Conditions[14] |
| Min | Max | Unit |
VDR | VCC for Data Retention |
|
| 2.0 |
| V |
ICCDR | Data Retention Current | VCC = VDR = 2.0V, | Ind’l |
| 10 | mA |
|
| CE > VCC – 0.3V, |
|
|
|
|
|
| Auto |
| 15 | mA | |
|
| VIN > VCC – 0.3V or VIN < 0.3V |
|
|
| |
|
|
|
|
|
| |
tCDR[6] | Chip Deselect to Data Retention Time |
|
| 0 |
| ns |
t [15] | Operation Recovery Time |
|
| t |
| ns |
R |
|
|
| RC |
|
|
Data Retention Waveform
|
| DATA RETENTION MODE |
|
VCC | 3.0V | VDR > 2V | 3.0V |
| tCDR |
| tR |
CE |
|
|
|
Switching Waveforms
Figure 4. Read Cycle No. 1[16, 17]
tRC
ADDRESS
tAA
tOHA
DATA OUT | PREVIOUS DATA VALID |
DATA VALID
Notes
12.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
13.The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
14.No input may exceed VCC + 0.3V.
15.Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 μs or stable at VCC(min.) > 50 μs.
16.Device is continuously selected. OE, CE, BHE, and BHE = VIL.
17.WE is HIGH for read cycle.
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