Cypress , CY7C09079V/89V/99V CY7C09179V/89V/99V

CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 7 of 21
Notes
14.Test conditions used are Load 2.
15.This parameter is guaranteed by design, but it is not production tested.
Switching Characteristics Over the Operating Range
Parameter Description
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Unit
-6[1] -7[1] -9 -12
Min Max Min Max Min Max Min Max
fMAX1 fMax Flow-Through 53 45 40 33 MHz
fMAX2 fMax Pipelined 100 83 67 50 MHz
tCYC1 Clock Cycle Time - Flow-Through 19 22 25 30 ns
tCYC2 Clock Cycle Time - Pipelined 10 12 15 20 ns
tCH1 Clock HIGH Time - Flow-Through 6.5 7.5 12 12 ns
tCL1 Clock LOW Time - Flow-Through 6.5 7.5 12 12 ns
tCH2 Clock HIGH Time - Pipelined 4 5 6 8 ns
tCL2 Clock LOW Time - Pipelined 4 5 6 8 ns
tRClock Rise Time 3 3 3 3 ns
tFClock Fall Time 3 3 3 3 ns
tSA Address Set-Up Time 3.5 4 4 4 ns
tHA Address Hold Time 0 0 1 1 ns
tSC Chip Enable Set-Up Time 3.5 4 4 4 ns
tHC Chip Enable Hold Time 0 0 1 1 ns
tSW R/W Set-Up Time 3.5 4 4 4 ns
tHW R/W Hold Time 0 0 1 1 ns
tSD Input Data Set-Up Time 3.5 4 4 4 ns
tHD Input Data Hold Time 0 0 1 1 ns
tSAD ADS Set-Up Time 3.5 4 4 4 ns
tHAD ADS Hold Time 0 0 1 1 ns
tSCN CNTEN Set-Up Time 3.5 4.5 5 5 ns
tHCN CNTEN Hold Time 0 0 1 1 ns
tSRST CNTRST Set-Up Time 3.5 4 4 4 ns
tHRST CNTRST Hold Time 0 0 1 1 ns
tOE Output Enable to Data Valid 8 9 10 12 ns
tOLZ[14, 15] OE to Low Z 2 2 2 2 ns
tOHZ[14, 15] OE to High Z 1 7 1 7 1 7 1 7 ns
tCD1 Clock to Data Valid - Flow-Through 15 18 20 25 ns
tCD2 Clock to Data Valid - Pipelined 6.5 7.5 912 ns
tDC Data Output Hold After Clock HIGH 2 2 2 2 ns
tCKHZ[14, 15] Clock HIGH to Output High Z 2 9 2 9 2 9 2 9 ns
tCKLZ[14, 15] Clock HIGH to Output Low Z 2 2 2 2 ns
Port to Port Delays
tCWDD Write Port Clock HIGH to Read Data Delay 30 35 40 40 ns
tCCS Clock to Clock Set-Up Time 9 10 15 15 ns
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