CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 4 of 21
Notes
8. This pin is NC for CY7C09179V.
9. This pin is NC for CY7C09179V and CY7C09189V
Selection Guide
Description CY7C09079V/89V/99V
CY7C09179V/89V/99V-6[1] CY7C09079V/89V/99V
CY7C09179V/89V/99V-7[1]
CY7C09079V/89V/99V
CY7C09179V/89V/99V
-9
CY7C09079V/89V/99V
CY7C09179V/89V/99V
-12
fMAX2 (MHz)
(Pipelined)
100 83 67 50
Max. Access Time
(ns) (Clock to Data,
Pipelined)
6.5 7.5 9 12
Typical Operating
Current ICC (mA)
175 155 135 115
Typical Standby
Current for ISB1
(mA) (Both Ports
TTL Level)
25 25 2 0 20
Typical Standby
Current for ISB3
(μA) (Both Ports
CMOS Level)
10 μA 10 μA10 μA 10 μA
Pin Definitions
Left Port Right Port Description
A0L–A16L A0R–A16R Address Inputs (A0–A14 for 32K; A0–A15 for 64K; and A0–A16 for 128K devices).
ADSLADSRAddress Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads
the burst counter with the address present on the address pins.
CE0L,CE1L CE0R,CE1R Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKLCLKRClock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENLCNTENRCounter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are
asserted LOW.
CNTRSTLCNTRSTRCounter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O8L I/O0R–I/O8R Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices).
OELOEROutput Enable Input. This signal must be asserted LOW to enable the I/O data pins during
read operations.
R/WLR/WRRead/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPELFT/PIPERFlow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND Ground Input.
NC No Connect.
VCC Power Input.
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