Cypress Selection Guide, Pin Definitions, Description CY7C09079V/89V/99V, CY7C09179V/89V/99V

CY7C09079V/89V/99V

CY7C09179V/89V/99V

Selection Guide

Description	CY7C09079V/89V/99V	CY7C09079V/89V/99V	CY7C09079V/89V/99V	CY7C09079V/89V/99V
	CY7C09179V/89V/99V-6[1]	CY7C09179V/89V/99V-7[1]	CY7C09179V/89V/99V	CY7C09179V/89V/99V
			-9	-12
fMAX2 (MHz)	100	83	67	50
(Pipelined)
Max. Access Time	6.5	7.5	9	12
(ns) (Clock to Data,
Pipelined)
Typical Operating	175	155	135	115
Current ICC (mA)
Typical Standby	25	25	20	20
Current for ISB1
(mA) (Both Ports
TTL Level)
Typical Standby	10 μA	10 μA	10 μA	10 μA
Current for ISB3
(μA) (Both Ports
CMOS Level)

Pin Definitions

			Left Port	Right Port				Description
A0L–A16L				A0R–A16R				Address Inputs (A0–A14for 32K; A0–A15for 64K; and A0–A16for 128K devices).
ADSL				ADSR				Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
								access the part using an externally supplied address. Asserting this signal LOW also loads
								the burst counter with the address present on the address pins.
	0L,CE1L				0R,CE1R			Chip Enable Input. To select either the left or right port, both		0 AND CE1 must be asserted
CE				CE					CE
								to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKL				CLKR				Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL				CNTENR				Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
								respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are
								asserted LOW.
CNTRSTL				CNTRSTR				Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
								respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O8L				I/O0R–I/O8R				Data Bus Input/Output (I/O0–I/O7for x8 devices; I/O0–I/O8for x9 devices).
		L				R		Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during
OE				OE
								read operations.
			L				R	Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
R/W				R/W
								For read operations, assert this pin HIGH.
								Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
FT/PIPEL
				FT/PIPER
								For pipelined mode operation, assert this pin HIGH.
GND								Ground Input.
NC								No Connect.
VCC								Power Input.

Notes

8.This pin is NC for CY7C09179V.

9.This pin is NC for CY7C09179V and CY7C09189V

Document #: 38-06043 Rev. *C Page 4 of 21

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