CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 16 of 21
Figure 17. Counter Reset (Pipelined Outputs)[19, 26, 32, 33]
Notes
32.CE0 = VIL; CE1 = VIH.
33.No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT Q0Q1Qn
D0
AX01A
nAn+1
tSAD tHAD
tSCN tHCN
tSRST tHRST
tSD tHD
tSW tHW
AnAn+1
tSA tHA
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
[+] Feedback