Contents
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CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
Features
Logic Block Diagram
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Functional Description
Pin Configurations
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Pin Configurations
Selection Guide
Pin Definitions
Maximum Ratings
Operating Range
Electrical Characteristics
Capacitance
Document #: 38-06043 Rev. *C Page 6 of 21
Figure 4. AC Test Loads (Applicable to -6 and -7 only)
(a) Load 1 (-6 and -7 only)
(b) Thvenin Eq uivalent (Load 1) (c)Three-State Delay(Load2)
(a)Normal Load(Load 1)
CY7C09079V/89V/99V CY7C09179V/89V/99V
Switching Characteristics
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CY7C09079V/89V/99V CY7C09179V/89V/99V
Figure 6. Read Cycle for Flow-Through Output (FT/PIPE = VIL)[16, 17, 18, 19]
CY7C09079V/89V/99V CY7C09179V/89V/99V
Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18, 19]
Figure 8. Bank Select Pipelined Read
Figure 9. Left Port Write to Flow-Through Right Port Read
Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL)[19, 26, 27, 28]
Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)[19, 26, 27, 28]
Figure 12. Flow-Through Read-to-Write-to-Read (OE = VIL)[17, 19, 26, 27, 28]
Figure 13. Flow-Through Read-to-Write-to-Read (OE Controlled)[17, 20, 26, 27, 28]
Figure 14. Pipelined Read with Address Counter Advance
Figure 15. Flow-Through Read with Address Counter Advance
Figure 16. Write with Address Counter Advance (Flow-Through or Pipelined Outputs)
Figure 17. Counter Reset (Pipelined Outputs)
CY7C09179V/89V/99V
Ordering Information
32K x8 3.3V Synchronous Dual-Port SRAM
64K x8 3.3V Synchronous Dual-Port SRAM
128K x8 3.3V Synchronous Dual-Port SRAM
32K x9 3.3V Synchronous Dual-Port SRAM
64K x9 3.3V Synchronous Dual-Port SRAM
128K x9 3.3V Synchronous Dual-Port SRAM
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