Cypress CY7C09079V, CY7C09089V, CY7C09099V, CY7C09179V, CY7C09189V, CY7C09199V Figure 9. Left Port Write to Flow-Through Right Port Read

CY7C09079V/89V/99V

CY7C09179V/89V/99V

Document #: 38-06043 Rev. *C Page 10 of 21

Figure 9. Left Port Write to Flow-Through Right Port Read[22, 23, 24, 25]

Notes

20.In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1)

= ADDRESS(B2).

21.OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.

22.The same waveforms apply for a right port write to flow-through left port read.

23.CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.

24.OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.

25.It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid

until tCCS + tCD1. tCWDD does not apply in this case.

Switching Waveforms (continued)

tSA tHA

tSW tHW

tSD tHD

MATCH

VALID

tCCS

tSW tHW

tDC

tCWDD

tCD1

MATCH

tSA tHA

MATCH

NO

MATCH

NO

VALID VALID

tDC

tCD1

CLKL

R/WL

ADDRESSL

DATAINL

ADDRESSR

DATAOUTR

CLKR

R/WR

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Contents

Main CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features Logic Block Diagram Document #: 38-06043 Rev. *C Page 2 of 21 Functional Description Pin Configurations Document #: 38-06043 Rev. *C Page 3 of 21 Pin Configurations Selection Guide Pin Definitions Maximum Ratings Operating Range Electrical Characteristics Capacitance Document #: 38-06043 Rev. *C Page 6 of 21 Figure 4. AC Test Loads (Applicable to -6 and -7 only) (a) Load 1 (-6 and -7 only) (b) Thvenin Eq uivalent (Load 1) (c)Three-State Delay(Load2) (a)Normal Load(Load 1) CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Characteristics Document #: 38-06043 Rev. *C Page 8 of 21 CY7C09079V/89V/99V CY7C09179V/89V/99V Figure 6. Read Cycle for Flow-Through Output (FT/PIPE = VIL)[16, 17, 18, 19] CY7C09079V/89V/99V CY7C09179V/89V/99V Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18, 19] Figure 8. Bank Select Pipelined Read Figure 9. Left Port Write to Flow-Through Right Port Read Figure 10. Pipelined Read-to-Write-to-Read (OE = VIL)[19, 26, 27, 28] Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)[19, 26, 27, 28] Figure 12. Flow-Through Read-to-Write-to-Read (OE = VIL)[17, 19, 26, 27, 28] Figure 13. Flow-Through Read-to-Write-to-Read (OE Controlled)[17, 20, 26, 27, 28] Figure 14. Pipelined Read with Address Counter Advance Figure 15. Flow-Through Read with Address Counter Advance Figure 16. Write with Address Counter Advance (Flow-Through or Pipelined Outputs) Figure 17. Counter Reset (Pipelined Outputs) CY7C09179V/89V/99V Ordering Information 32K x8 3.3V Synchronous Dual-Port SRAM 64K x8 3.3V Synchronous Dual-Port SRAM 128K x8 3.3V Synchronous Dual-Port SRAM 32K x9 3.3V Synchronous Dual-Port SRAM 64K x9 3.3V Synchronous Dual-Port SRAM 128K x9 3.3V Synchronous Dual-Port SRAM Page Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions