Cypress CY7C09199V, CY7C09179V, CY7C09099V, CY7C09089V Functional Description, Pin Configurations

CY7C09079V/89V/99V

CY7C09179V/89V/99V

Functional Description

The CY7C09079V/89V/99V and CY7C09179V/89V/99V are high speed synchronous CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[4] Registers on control, address, and data lines enable minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode, data is available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin.

Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to enable the shortest possible cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables enables easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs.

Counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe (ADS). When the port’s Count Enable (CNTEN) is asserted, the address counter increments on each LOW-to-HIGH transition of that port’s clock signal. This reads/writes one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and loops back to the start. Counter Reset (CNTRST) is used to reset the burst counter.

All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.

Pin Configurations

Figure 1. 100-Pin TQFP (Top View) - CY7C09099V (128K x 8), CY7C09089V (64K x 8),CY7C09079V (32K x 8)

							NC		NC		A6L		A5L	A4L		A3L		A2L		A1L	A0L		CNTENL		CLKL		ADSL	GND		ADSR		CLKR		CNTENR		A0R		A1R		A2R		A3R		A4R		A5R		A6R		NC		NC
						100 99				98		97		96	95		94		93		92	91		90		89		88	87		86		85		84		83		82		81		80		79		78		77		76
					NC	1																																													75		NC
					NC	2																																													74		NC
				A7L		3																																													73		A7R
				A8L		4																																													72		A8R
				A9L		5																																													71		A9R
			A10L			6																																													70		A10R
			A11L			7																																													69		A11R
			A12L			8																																													68		A12R
			A13L			9																																													67		A13R
			A14L			10																																													66		A14R
[5]			A15L			11																																													65		A15R [5]
[6]			A16L			12																																													64		A16R [6]
			VCC			13																																													63		GND
					NC	14																																													62		NC
					NC	15																																													61		NC
					NC	16																																													60		NC
					NC	17																																													59		NC
						18																																													58
			CE0L																																																		CE0R
			CE1L			19																																													57		CE1R
						20
	CNTRSTL																																																		56		CNTRSTR
						21
			R/WL																																																55		R/WR
						22
[7]				OEL																																															54		OER
						23																																															FT/PIPER [7]
		FT/PIPEL																																																	53
					NC	24																																													52		GND
					NC	25																																													51		NC
						26		27		28		29		30	31		32		33		34	35		36		37		38	39		40		41		42		43		44		45		46		47		48		49		50
							GND		NC		I/O7L		I/O6L	I/O5L		I/O4L		I/O3L		I/O2L	GND		I/O1L		I/O0L		VCC	GND		I/O0R		I/01R		I/O2R		VCC		I/O3R		I/O4R		I/O5R		I/O6R		I/O7R		NC		NC		NC

Notes

4.When writing simultaneously to the same location, the final value cannot be guaranteed.

5.This pin is NC for CY7C09079V.

6.This pin is NC for CY7C09079V and CY7C09089V.

7.For CY7C09079V and CY7C09089V, pin #23 connected to VCC is pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is pin compatible with an IDT 5V x16 flow-through device.

Document #: 38-06043 Rev. *C Page 2 of 21

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