Cypress CY7C1217H Read/Write Timing

CY7C1217H

Document #: 38-05670 Rev. *B Page 13 of 16

Read/Write Timing[16, 18, 19]

Notes:

18.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

19.GW is HIGH.

Timing Diagrams (continued)

CYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

Single WRITE

D(A3)

A3 A4

BURST READBack-to-Back READs

High-Z

Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

tWEH

tWES

tOEHZ

tDH

tDS

tCDV

tOELZ

A1 A5 A6

D(A5) D(A6)

Q(A1)

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

ADSP

ADSC

BWE, BW[A:D]

ADV

Data In (D)

Data Out (Q)

[+] Feedback

Contents

Main CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAM Features Functional Description Selection Guide CY7C1217H Logic Block Diagram ZZ MODE A ADDRESS REGISTER CY7C1217H Pin Descriptions Functional Overview Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table CY7C1217H Truth Table for Read/Write Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Timing Diagrams Read Cycle Timing CY7C1217H Write Cycle Timing Read/Write Timing ZZ Mode Timing Ordering Information Package Diagram A Document History Page