CY7C1217H

ZZ Mode Electrical Characteristics

Parameter

 

Description

 

 

 

 

 

 

 

Test Conditions

 

 

Min.

 

 

Max.

Unit

 

IDDZZ

Sleep mode standby current

 

 

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

 

 

40

 

mA

 

tZZS

Device operation to ZZ

 

 

 

 

 

 

 

ZZ > VDD – 0.2V

 

 

 

 

 

 

 

 

 

 

2tCYC

ns

 

tZZREC

ZZ recovery time

 

 

 

 

 

 

 

ZZ < 0.2V

 

 

 

 

 

 

2tCYC

 

 

 

 

 

ns

 

tZZI

ZZ Active to sleep current

 

 

 

 

 

This parameter is sampled

 

 

 

 

 

 

 

2tCYC

ns

 

tRZZI

ZZ Inactive to exit sleep current

 

 

 

This parameter is sampled

 

 

0

 

 

 

 

 

 

 

ns

 

Truth Table [2, 3, 4, 5, 6]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cycle Description

Used

 

CE1

CE2

 

CE3

ZZ

ADSP

 

ADSC

 

 

ADV

 

 

WRITE

 

OE

 

CLK

 

DQ

 

Deselected Cycle,

None

 

H

X

 

X

 

L

 

X

 

L

 

 

X

 

 

X

 

X

 

L-H

 

Tri-State

 

Power-down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle,

None

 

L

L

 

X

 

L

 

L

 

X

 

 

X

 

 

X

 

X

 

L-H

 

Tri-State

 

Power-down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle,

None

 

L

X

 

H

 

L

 

L

 

X

 

 

X

 

 

X

 

X

 

L-H

 

Tri-State

 

Power-down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle,

None

 

L

L

 

X

 

L

 

H

 

L

 

 

X

 

 

X

 

X

 

L-H

 

Tri-State

 

Power-down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle,

None

 

X

X

 

X

 

L

 

H

 

L

 

 

X

 

 

X

 

X

 

L-H

 

Tri-State

 

Power-down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode, Power-down

None

 

X

X

 

X

 

H

 

X

 

X

 

 

X

 

 

X

 

X

 

X

 

Tri-State

 

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

L

 

X

 

 

X

 

 

X

 

 

L

 

L-H

 

Q

 

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

L

 

X

 

 

X

 

 

X

 

H

 

L-H

 

Tri-State

 

Write Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

H

 

L

 

 

X

 

 

L

 

X

 

L-H

 

D

 

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

H

 

L

 

 

X

 

 

H

 

 

L

 

L-H

 

Q

 

Read Cycle, Begin Burst

External

 

L

H

 

L

 

L

 

H

 

L

 

 

X

 

 

H

 

H

 

L-H

 

Tri-State

 

Read Cycle, Continue Burst

Next

 

X

X

 

X

 

L

 

H

 

H

 

 

L

 

 

H

 

 

L

 

L-H

 

Q

 

Read Cycle, Continue Burst

Next

 

X

X

 

X

 

L

 

H

 

H

 

 

L

 

 

H

 

H

 

L-H

 

Tri-State

 

Read Cycle, Continue Burst

Next

 

H

X

 

X

 

L

 

X

 

H

 

 

L

 

 

H

 

 

L

 

L-H

 

Q

 

Read Cycle, Continue Burst

Next

 

H

X

 

X

 

L

 

X

 

H

 

 

L

 

 

H

 

H

 

L-H

 

Tri-State

 

Write Cycle, Continue Burst

Next

 

X

X

 

X

 

L

 

H

 

H

 

 

L

 

 

L

 

X

 

L-H

 

D

 

Write Cycle, Continue Burst

Next

 

H

X

 

X

 

L

 

X

 

H

 

 

L

 

 

L

 

X

 

L-H

 

D

 

Read Cycle, Suspend Burst

Current

 

X

X

 

X

 

L

 

H

 

H

 

 

H

 

 

H

 

 

L

 

L-H

 

Q

 

Read Cycle, Suspend Burst

Current

 

X

X

 

X

 

L

 

H

 

H

 

 

H

 

 

H

 

H

 

L-H

 

Tri-State

 

Read Cycle, Suspend Burst

Current

 

H

X

 

X

 

L

 

X

 

H

 

 

H

 

 

H

 

 

L

 

L-H

 

Q

 

Read Cycle, Suspend Burst

Current

 

H

X

 

X

 

L

 

X

 

H

 

 

H

 

 

H

 

H

 

L-H

 

Tri-State

 

Write Cycle, Suspend Burst

Current

 

X

X

 

X

 

L

 

H

 

H

 

 

H

 

 

L

 

X

 

L-H

 

D

 

Write Cycle, Suspend Burst

Current

 

H

X

 

X

 

L

 

X

 

H

 

 

H

 

 

L

 

X

 

L-H

 

D

 

Notes:

2.X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3.WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA, BWB, BWC, BWD), BWE, GW = H.

4.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5.The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the Write cycle.

6.OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 38-05670 Rev. *B

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Cypress CY7C1217H manual ZZ Mode Electrical Characteristics, Parameter Description Test Conditions Min Max Unit

CY7C1217H specifications

The Cypress CY7C1217H is a high-performance synchronous static random-access memory (SRAM) device that offers an array of features making it suitable for a diverse range of applications. With a configuration of 1 Meg x 16 bits, this component is well-suited for use in high-speed data processing systems, instrumentation, networking, and other applications that demand rapid-read and write cycles.

One of the standout features of the CY7C1217H is its high-speed operation. It supports a clock frequency of up to 167 MHz, making it ideal for systems that require fast data access and transfer rates. This high-speed capability is complemented by a low-power consumption profile, which is critical for battery-operated devices and energy-efficient applications. The part operates on a supply voltage of 1.65V to 1.95V, allowing for compatibility with modern low-voltage digital systems.

The device utilizes a dual-port architecture, enabling simultaneous access from multiple processors or data buses. This dual-port design significantly improves performance by allowing multiple data transactions to occur simultaneously, thus increasing overall system throughput. Additionally, the CY7C1217H features an asynchronous read and write capability, allowing for flexible operation in various system configurations.

In terms of memory organization, the CY7C1217H employs a multiplexed address input design, which helps optimize pin count and leads to more efficient PCB layouts. The use of a XY address decoding scheme allows for straightforward integration into existing systems while maintaining high performance.

Another notable characteristic of this SRAM is its reliability and durability. The device is built using Cypress's advanced trench technology, providing inherent robustness against environmental stress factors. This ensures a longer lifespan and improved performance consistency over time.

Furthermore, the CY7C1217H supports a range of operating temperatures, making it suitable for both commercial and industrial applications. Whether used in consumer electronics or critical industrial control systems, this SRAM's versatility ensures it can meet diverse design requirements.

In summary, the Cypress CY7C1217H synchronous SRAM combines high-speed performance, low power consumption, and dual-port capabilities with robust design characteristics. Its versatility and reliability make it an excellent choice for engineers looking to enhance their high-performance applications across various sectors.