CY7C1307BV25
CY7C1305BV25
Document #: 38-05630 Rev. *A Page 18 of 21
Switching Characteristics Over the Operating Range[23]
Cypress
Parameter Consortium
Parameter Description
167 MHz
UnitMin. Max.
tPower[24] VCC (typical) to the First Access Read or Write 10 µs
Cycle Time
tCYC tKHKH K Clock and C Clock Cycle Time 6.0 ns
tKH tKHKL Input Clock (K/K and C/C) HIGH 2.4 ns
tKL tKLKH Input Clock (K/K and C/C) LOW 2.4 ns
tKHKHtKHKHK/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge
to rising edge) 2.7 3.3 ns
tKHCH tKHCH K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 2.0 ns
Set-up Times
tSA tSA Address Set-up to Clock (K and K) Rise 0.7 ns
tSC tSC Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0, BWS1)0.7 ns
tSD tSD D[x:0] Set-up to Clock (K and K) Rise 0.7 ns
Hold Times
tHA tHA Address Hold after Clock (K and K) Rise 0.7 ns
tHC tHC Control Signals Hold after Clock (K and K) Rise
(RPS, WPS, BWS0, BWS1)0.7 ns
tHD tHD D[x:0] Hold after Clock (K and K) Rise 0.7 ns
Output Times
tCO tCHQV C/C Clock Rise (or K/K in single clock mode) to Data Valid[25] 2.5 ns
tDOH tCHQX Data Output Hold after Output C/C Clock Rise (Active to Active) 1.2 ns
tCHZ tCHZ Clock (C and C) rise to High-Z (Active to High-Z)[25, 26] 2.5 ns
tCLZ tCLZ Clock (C and C) rise to Low-Z[25, 26] 1.2 ns
Notes:
23.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,VREF = 0.75V, RQ = 250, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
24.This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a Read
or Write operation can be initiated.
25.At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO.
26.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
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