Cypress CY7C1324H Timing Diagrams continued, Read/Write Timing15, 17, + Feedback, QA4+2 QA4+3

Models: CY7C1324H

1 15

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CY7C1324H

Timing Diagrams (continued)

tCYC

CLK

CH CL

tADS tADH

ADSP

ADSC

tAS tAH

Notes:

17.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

A5 A6

D(A5) D(A6)

Back-to-Back WRITEs

Document #: 001-00208 Rev. *B

Page 12 of 15

[+] Feedback

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Contents

Features Logic Block DiagramCY7C1324H Functional Description1Pin Configurations Selection Guide15CY7C1324H CY7C1324HPin Definitions CY7C1324HFunctional Overview Burst SequencesSleep Mode Interleaved Burst Address Table MODE = Floating or VDDZZ Mode Electrical Characteristics CY7C1324HTruth Table for Read/Write 2 CY7C1324HFunction Maximum Ratings Operating RangeElectrical Characteristics Over the Operating Range 6 CY7C1324HCapacitance8 Thermal Resistance8AC Test Loads and Waveforms CY7C1324HSwitching Characteristics Over the Operating Range9 CY7C1324HTiming Diagrams CY7C1324HRead Cycle Timing15 + FeedbackTiming Diagrams continued CY7C1324HWrite Cycle Timing15 + FeedbackTiming Diagrams continued CY7C1324HRead/Write Timing15, 17 + FeedbackTiming Diagrams continued 20. DQs are in High-Z when exiting ZZ sleep modeCY7C1324H ZZ Mode Timing19Package Diagram Ordering InformationCY7C1324H CommercialDocument History Page Issue DateCY7C1324H Document Title CY7C1324H 2-Mbit 128K x 18 Flow-Through Sync SRAM