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Cypress CY7C1324H manual Timing Diagrams continued, ZZ Mode Timing19, + Feedback

Models: CY7C1324H

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CY7C1324H

Timing Diagrams (continued)

ZZMode Timing[19, 20]

CLK

t ZZ

t ZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

Outputs (Q)

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

Notes:

19.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

20.DQs are in High-Z when exiting ZZ sleep mode.

Document #: 001-00208 Rev. *B

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Cypress CY7C1324H Timing Diagrams continued, ZZ Mode Timing19, + Feedback, DQs are in High-Z when exiting ZZ sleep mode

Contents

Logic Block Diagram FeaturesCY7C1324H Functional Description1Selection Guide Pin Configurations15CY7C1324H CY7C1324HCY7C1324H Pin DefinitionsBurst Sequences Functional OverviewSleep Mode Interleaved Burst Address Table MODE = Floating or VDDCY7C1324H ZZ Mode Electrical CharacteristicsCY7C1324H Truth Table for Read/Write 2Function Operating Range Maximum RatingsElectrical Characteristics Over the Operating Range 6 CY7C1324HThermal Resistance8 Capacitance8AC Test Loads and Waveforms CY7C1324HCY7C1324H Switching Characteristics Over the Operating Range9CY7C1324H Timing DiagramsRead Cycle Timing15 + FeedbackCY7C1324H Timing Diagrams continuedWrite Cycle Timing15 + FeedbackCY7C1324H Timing Diagrams continuedRead/Write Timing15, 17 + Feedback20. DQs are in High-Z when exiting ZZ sleep mode Timing Diagrams continuedCY7C1324H ZZ Mode Timing19Ordering Information Package DiagramCY7C1324H CommercialIssue Date Document History PageCY7C1324H Document Title CY7C1324H 2-Mbit 128K x 18 Flow-Through Sync SRAM