Cypress CY7C1324H manual Timing Diagrams, Read Cycle Timing15, + Feedback

Models: CY7C1324H

1 15

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CY7C1324H

tCYC

CLK

t CH

tADS tADH

t CL

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS

GW, BWE,BW[A:B]

ADV

Note:

15. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 001-00208 Rev. *B

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Contents

CY7C1324H FeaturesLogic Block Diagram Functional Description115CY7C1324H Pin ConfigurationsSelection Guide CY7C1324HPin Definitions CY7C1324HSleep Mode Functional OverviewBurst Sequences Interleaved Burst Address Table MODE = Floating or VDDZZ Mode Electrical Characteristics CY7C1324HCY7C1324H Truth Table for Read/Write 2Function Electrical Characteristics Over the Operating Range 6 Maximum RatingsOperating Range CY7C1324HAC Test Loads and Waveforms Capacitance8Thermal Resistance8 CY7C1324HSwitching Characteristics Over the Operating Range9 CY7C1324HRead Cycle Timing15 Timing DiagramsCY7C1324H + FeedbackWrite Cycle Timing15 Timing Diagrams continuedCY7C1324H + FeedbackRead/Write Timing15, 17 Timing Diagrams continuedCY7C1324H + FeedbackCY7C1324H Timing Diagrams continued20. DQs are in High-Z when exiting ZZ sleep mode ZZ Mode Timing19CY7C1324H Package DiagramOrdering Information CommercialCY7C1324H Document History PageIssue Date Document Title CY7C1324H 2-Mbit 128K x 18 Flow-Through Sync SRAM