CY7C1329H
Switching Waveforms (continued)
Write Cycle Timing[17, 18]
CLK
ADSP
ADSC
ADDRESS
BWE,
BW[A :D]
GW
CE
ADV
OE
Data In (D)
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| tCYC |
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| tCH | tCL |
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tADS | tADH |
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| tADS | tADH | ADSC extends burst |
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| tADS | tADH | ||
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tAS | tAH |
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| A1 |
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| A2 | A3 |
| Byte write signals are |
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| ignored for first cycle when |
| tWES tWEH | ||
| ADSP initiates burst |
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tWES tWEH
tCES | tCEH |
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| tADVS tADVH |
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| ADV suspends burst |
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| tDS tDH |
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D(A1) | D(A2) | D(A2 + 1) | D(A2 + 1) | D(A2 + 2) | D(A2 + 3) | D(A3) | D(A3 + 1) | D(A3 + 2) | |
| t |
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| OEHZ |
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Data Out (Q)
BURST READ
Single WRITE
| BURST WRITE |
DON’T CARE | UNDEFINED |
Extended BURST WRITE
Note:
18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A : D] LOW.
Document #: | Page 12 of 16 |
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