Cypress CY7C1329H CY7C1329H

CY7C1329H

Document #: 38-05673 Rev. *B Page 7 of 16

Write Bytes D, A H L L H H L

Write Bytes D, B H L L H L H

Write Bytes D, B, A H L L H L L

Write Bytes D, C H L L L H H

Write Bytes D, C, A H L L L H L

Write Bytes D, C, B HLLLLH

Write All Bytes HLLLLL

Write All Bytes LXXXXX

Truth Table for Read/Write (continued)[2, 3]

Function GW BWE BWDBWCBWBBWA

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Contents

Main 2-Mbit (64K x 32) Pipelined Sync SRAM CY7C1329H Features Functional Description Logic Block Diagram CY7C1329H Pin Configuration CY7C1329H Selection Guide 100-pin TQFP Pinout CY7C1329H Pin Definitions Functional Overview Burst Sequences Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write CY7C1329H Truth Table for Read/Write Maximum Ratings Operating Range Electrical Characteristics CY7C1329H Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing CY7C1329H Read/Write Cycle Timing Page Ordering Information Package Diagram A Document History Page