Cypress CY7C1329H

CY7C1329H

Document #: 38-05673 Rev. *B Page 14 of 16

ZZ Mode Timing[21, 22]

Notes:

21.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

22.DQs are in High-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

[+] Feedback

Contents

Main 2-Mbit (64K x 32) Pipelined Sync SRAM CY7C1329H Features Functional Description Logic Block Diagram CY7C1329H Pin Configuration CY7C1329H Selection Guide 100-pin TQFP Pinout CY7C1329H Pin Definitions Functional Overview Burst Sequences Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write CY7C1329H Truth Table for Read/Write Maximum Ratings Operating Range Electrical Characteristics CY7C1329H Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing CY7C1329H Read/Write Cycle Timing Page Ordering Information Package Diagram A Document History Page