Cypress CY7C1329H CY7C1329H

CY7C1329H
Document #: 38-05673 Rev. *B Page 13 of 16
Read/Write Cycle Timing[17, 19, 20]
Notes:
19.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
20.GW is HIGH.
Switching Waveforms (continued)
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A2
tCEH
tCES
BWE,
BW[A:D]
D
ata Out (Q) High-Z
ADV
Single WRITE
D(A3)
A4 A5 A6
D(A5) D(A6)
Data In (D)
BURST READBack-to-Back READs
High-Z
Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)
tWEH
tWES
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
tCLZ
tCO
Back-to-Back
WRITEs
A1
DON’T CARE UNDEFINED
A3
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