NOP, STALL, and Deselect Cycles18, 19, DA4

CY7C1334H

NOP, STALL, and Deselect Cycles[18, 19, 21]

BW[A:D]

In-Out (DQ)

WRITE

D(A1)

READ Q(A2)

STALL

READ Q(A3)

WRITE

D(A4)

STALL

NOP

READ Q(A5)

DESELECT

CONTINUE DESELECT

CLK

t ZZ

t ZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

Outputs (Q)

Notes:

High-Z

t ZZREC

t RZZI

DESELECT or READ Only

21.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

22.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

23.I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05678 Rev. *B

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Contents

Cypress Semiconductor Corporation FeaturesLogic Block Diagram 166 MHz 133 MHz Unit Pin ConfigurationMaximum Access Time tCO Maximum Operating Current IDD Selection Guide Pin Definitions Functional Overview ADV/LD CEN CLK Interleaved Burst Address Table Mode = Floating or VDDFirst Second Third Fourth Address A1, A0 First Second Third Fourth Address A1, A0 Operation Used BW D BW C BW B BW a ZZ Mode Electrical CharacteristicsWrite Cycle Description2 Function Ambient Range Maximum RatingOperating Range AC Test Loads and Waveforms Capacitance11Thermal Resistance11 Switching Characteristics Over the Operating Range 12 DON’T Care Switching WaveformsRead/Write Timing18, 19 Address A1 A2 DA4 ZZ Mode Timing22NOP, STALL, and Deselect Cycles18, 19 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramOrdering Information REV ECN no Issue Date Orig. Description of ChangeDocument History