
CY7C1334H
Interleaved Burst Address Table (MODE = Floating or VDD)
First | Second | Third | Fourth |
Address | Address | Address | Address |
A1, A0 | A1, A0 | A1, A0 | A1, A0 |
00 | 01 | 10 | 11 |
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01 | 00 | 11 | 10 |
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10 | 11 | 00 | 01 |
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11 | 10 | 01 | 00 |
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Cycle Description Truth Table[2, 3, 4, 5, 6, 7, 8]
Linear Burst Address Table (MODE = GND)
First | Second | Third | Fourth |
Address | Address | Address | Address |
A1, A0 | A1, A0 | A1, A0 | A1, A0 |
00 | 01 | 10 | 11 |
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01 | 10 | 11 | 00 |
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10 | 11 | 00 | 01 |
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11 | 00 | 01 | 10 |
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Operation | Used |
| CE |
| ZZ | ADV/LD |
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| WE |
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| BWx |
| OE |
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| CEN | CLK | DQ | |||
Deselect Cycle | None |
| H |
| L | L |
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| X |
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| X |
| X |
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| L | |||||
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Continue Deselect Cycle | None |
| X |
| L | H |
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| X |
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| X |
| X |
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| L | |||||
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Read Cycle (Begin Burst) | External |
| L |
| L | L |
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| H |
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| X |
| L |
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| L | Data Out (Q) | ||||
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Read Cycle (Continue Burst) | Next |
| X |
| L | H |
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| X |
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| X |
| L |
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| L | Data Out (Q) | ||||
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NOP/Dummy Read (Begin Burst) | External |
| L |
| L | L |
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| H |
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| X |
| H |
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| L | |||||
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Dummy Read (Continue Burst) | Next |
| X |
| L | H |
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| X |
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| X |
| H |
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| L | |||||
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Write Cycle (Begin Burst) | External |
| L |
| L | L |
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| L |
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| L |
| X |
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| L | Data In (D) | ||||
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Write Cycle (Continue Burst) | Next |
| X |
| L | H |
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| X |
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| L |
| X |
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| L | Data In (D) | ||||
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NOP/WRITE ABORT (Begin Burst) | None |
| L |
| L | L |
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| L |
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| H |
| X |
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| L | |||||
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WRITE ABORT (Continue Burst) | Next |
| X |
| L | H |
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| X |
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| H |
| X |
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| L | |||||
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IGNORE CLOCK EDGE (Stall) | Current |
| X |
| L | X |
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| X |
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| X |
| X |
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| H | - | ||||
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Sleep MODE | None |
| X |
| H | X |
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| X |
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| X |
| X |
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| X | X | ||||
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Notes:
2.X = “Don't Care.” H = HIGH, L = LOW. CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3.Write is defined by BW[A:D], and WE. See Write Cycle Descriptions table.
4.When a write cycle is detected, all I/Os are
5.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6.CEN = H, inserts wait states.
7.Device will
8.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] =
Document #: | Page 5 of 13 |
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