Cypress CY7C1344H CY7C1344H

CY7C1344H

Document #: 001-00211 Rev. *B Page 13 of 15

Notes:

20.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

21.DQs are in High-Z when exiting ZZ sleep mode.

Timing Diagrams (continued)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

[+] Feedback

Contents

Main 2-Mbit (64K x 36) Flow-Through Sync SRAM CY7C1344H Features Functional Description Logic Block Diagram CY7C1344H CY7C1344H Pin Definitions CY7C1344H Functional Overview Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write CY7C1344H Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Timing Diagrams Read Cycle Timing Document #: 001-00211 Rev. *B Page 11 of 15 Write Cycle Timing Read/Write Timing CY7C1344H ZZ Mode Timing [20, 21] Ordering Information Package Diagram A Document History Page