Cypress CY7C1344H manual Features, Logic Block Diagram Functional Description1

CY7C1344H

2-Mbit (64K x 36) Flow-Through Sync SRAM

Features

•64K x 36 common I/O

•3.3V core power supply

•3.3V/2.5V I/O supply

•Fast clock-to-output times

—6.5 ns (133-MHz version)

—8.0 ns (100-MHz version)

•Provide high-performance 2-1-1-1 access rate

•User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences

•Separate processor and controller address strobes

•Synchronous self-timed write

•Asynchronous output enable

•Offered in JEDEC-standard lead-free 100-pin TQFP package

•“ZZ” Sleep Mode option

Logic Block Diagram

Functional Description[1]

The CY7C1344H is a 64K x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is

6.5ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW[A:D] and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1344H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

The CY7C1344H operates from a +3.3V core power supply while all outputs may operate with either a +3.3V/2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

A0, A1, A ADDRESS

REGISTER

A[1:0]

MODE

ADV

CLK

ADSC

ADSP

BWD

BWC

BWB

BWA

BWE

GW

CE1

CE2

CE3

OE

ZZ

BURST	Q1
COUNTER
AND LOGIC
CLR	Q0
DQD, DQPD	DQD, DQPD
	BYTE
BYTE
	WRITE REGISTER
WRITE REGISTER
DQC, DQPC	DQC, DQPC
	BYTE
BYTE
	WRITE REGISTER
WRITE REGISTER		MEMORY		OUTPUT	DQs
			SENSE
		ARRAY		BUFFERS	DQPA
	DQB, DQPB		AMPS
DQB, DQPB					DQPB
	BYTE
					DQPC
BYTE	WRITE REGISTER
					DQPD
WRITE REGISTER
	DQA, DQPA
DQA, DQPA	BYTE
BYTE	WRITE REGISTER
WRITE REGISTER
				INPUT
ENABLE				REGISTERS
REGISTER
SLEEP
CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 001-00211 Rev. *B		Revised April 26, 2006

[+] Feedback