Write Cycle Timing16 | Cypress CY7C1344H instruction

CY7C1344H

Timing Diagrams (continued)

Write Cycle Timing[16, 17]

tCYC

CLK

tCH tCL

tADS tADH

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS A1 A2

Byte write signals are ignored for first cycle when

ADSP initiates burst.

BWE,

BW[A:D]

t t

WES WEH

ADSC extends burst.

tADS tADH

tWES tWEH

tCES tCEH

ADV

Data in (D)

High-Z

Data Out (Q)

tOEHZ

tDS t DH

D(A1)

tADVS tADVH

ADV suspends burst.

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

BURST READ

Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Note:

17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Document #: 001-00211 Rev. *B

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Cypress CY7C1344H manual Write Cycle Timing16

Contents

Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description1 133 MHz 100 MHz Unit Pin ConfigurationsSelection Guide 15CY7C1344H Pin Definitions Functional Overview Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Adsp Adsc ADV Write CLK ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Address Cycle Description Used BWE BW D BW C BW B BW a Truth Table for Read/Write2Function Description Test Conditions Min Max Unit Maximum RatingsOperating Range Ambient Range AC Test Loads and Waveforms Capacitance9Thermal Resistance9 Switching Characteristics Over the Operating Range 10 Adsc Timing DiagramsRead Cycle Timing16 CLK Write Cycle Timing16 Burst Read Read/Write Timing16, 18Adsp Adsc Address DON’T Care ZZ Mode Timing 20 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramOrdering Information PCI Issue Date Orig. Description of ChangeDocument History REV ECN no