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Cypress CY7C1344H Document #: 001-00211 Rev. *B Page 11 of 15, Write Cycle Timing

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CY7C1344H

Document #: 001-00211 Rev. *B Page 11 of 15

Write Cycle Timing[16, 17]

Note:

17.Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Timing Diagrams (continued)

tCYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

High-Z

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are ignored for first cycle when

ADSP initiates burst.

ADSC extends burst.

ADV suspends burst.

DON’T CARE UNDEFINED

ADSP

ADSC

BWE,

BW[A:D]

ADV

Data in (D)

ata Out (Q)

[+] Feedback

Contents

Main 2-Mbit (64K x 36) Flow-Through Sync SRAM CY7C1344H Features Functional Description Logic Block Diagram CY7C1344H CY7C1344H Pin Definitions CY7C1344H Functional Overview Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write CY7C1344H Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Timing Diagrams Read Cycle Timing Document #: 001-00211 Rev. *B Page 11 of 15 Write Cycle Timing Read/Write Timing CY7C1344H ZZ Mode Timing [20, 21] Ordering Information Package Diagram A Document History Page