Document History, REV ECN no, Pci, Nxr | Cypress CY7C1344H manual

CY7C1344H

Document History Page

Document Title: CY7C1344H 2-Mbit (64K x 36) Flow-Through Sync SRAM

Document Number: 001-00211

REV.	ECN NO.	Issue Date	Orig. of	Description of Change
REV.	ECN NO.	Issue Date	Change	Description of Change

**	347377	See ECN	PCI	New Data Sheet

*A	428408	See ECN	NXR	Changed address of Cypress Semiconductor Corporation on Page# 1 from
				“3901 North First Street” to “198 Champion Court”
				Changed Three-State to Tri-State.
				Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
				Electrical Characteristics Table.
				Modified test condition from VIH < VDD to VIH < VDD
				Replaced Package Name column with Package Diagram in the Ordering
				Information table.
				Replaced Package Diagram of 51-85050 from A to B
*B	459347	See ECN	NXR	Converted from Preliminary to Final
				Included 2.5V I/O option
				Updated the Ordering Information table.

Document #: 001-00211 Rev. *B

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Contents

Features Logic Block Diagram Functional Description1Cypress Semiconductor Corporation 133 MHz 100 MHz Unit Pin ConfigurationsSelection Guide 15CY7C1344H Pin Definitions Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDFunctional Overview Adsp Adsc ADV Write CLK ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Address Cycle Description Used Truth Table for Read/Write2 FunctionBWE BW D BW C BW B BW a Description Test Conditions Min Max Unit Maximum RatingsOperating Range Ambient Range Capacitance9 Thermal Resistance9AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 10 Adsc Timing DiagramsRead Cycle Timing16 CLK Write Cycle Timing16 Burst Read Read/Write Timing16, 18Adsp Adsc Address DON’T Care ZZ Mode Timing 20 Package Diagram Ordering InformationPin Tqfp 14 x 20 x 1.4 mm PCI Issue Date Orig. Description of ChangeDocument History REV ECN no