Cypress CY7C1352G manual Interleaved Burst Address Table Mode = Floating or VDD

CY7C1352G

Interleaved Burst Address Table (MODE = Floating or VDD)

First	Second	Third	Fourth
Address	Address	Address	Address
A1, A0	A1, A0	A1, A0	A1, A0
00	01	10	11
01	00	11	10
10	11	00	01
11	10	01	00

Linear Burst Address Table (MODE = GND)

First	Second	Third	Fourth
Address	Address	Address	Address
A1, A0	A1, A0	A1, A0	A1, A0
00	01	10	11
01	10	11	00
10	11	00	01
11	00	01	10

ZZ Mode Electrical Characteristics

Parameter	Description	Test Conditions	Min.	Max.	Unit
IDDZZ	Snooze mode standby current	ZZ > VDD − 0.2V		40	mA
tZZS	Device operation to ZZ	ZZ > VDD − 0.2V		2tCYC	ns
tZZREC	ZZ recovery time	ZZ < 0.2V	2tCYC		ns
tZZI	ZZ active to snooze current	This parameter is sampled		2tCYC	ns
tRZZI	ZZ inactive to exit snooze current	This parameter is sampled	0		ns

Truth Table [2, 3, 4, 5, 6, 7, 8]

	Address
Operation	Used	CE	ZZ	ADV/LD	WE	BWx	OE	CEN	CLK	DQ
Deselect Cycle	None	H	L	L	X	X	X	L	L-H	Tri-State
Continue Deselect Cycle	None	X	L	H	X	X	X	L	L-H	Tri-State
Read Cycle (Begin Burst)	External	L	L	L	H	X	L	L	L-H	Data Out (Q)
Read Cycle (Continue Burst)	Next	X	L	H	X	X	L	L	L-H	Data Out (Q)
NOP/Dummy Read (Begin Burst)	External	L	L	L	H	X	H	L	L-H	Tri-State
Dummy Read (Continue Burst)	Next	X	L	H	X	X	H	L	L-H	Tri-State
Write Cycle (Begin Burst)	External	L	L	L	L	L	X	L	L-H	Data In (D)
Write Cycle (Continue Burst)	Next	X	L	H	X	L	X	L	L-H	Data In (D)
NOP/WRITE ABORT (Begin Burst)	None	L	L	L	L	H	X	L	L-H	Tri-State
WRITE ABORT (Continue Burst)	Next	X	L	H	X	H	X	L	L-H	Tri-State
IGNORE CLOCK EDGE (Stall)	Current	X	L	X	X	X	X	H	L-H	–
SNOOZE MODE	None	X	H	X	X	X	X	X	X	Tri-State

Truth Table for Read/Write [2, 3]

Function			B		A
	WE	BW		BW
Read	H	X		X
Write − No bytes written	L	H		H
Write Byte A − (DQA and DQPA)	L	H		L
Write Byte B − (DQB and DQPB)	L	L		H
Write All Bytes	L	L		L

Notes:

2.X=”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for ALL Chip Enables active. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

3.Write is defined by BW[A:B], and WE. See Write Cycle Descriptions table.

4.When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

5.The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6.CEN = H, inserts wait states.

7.Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

8.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = tri-state when OE is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.

Document #: 38-05514 Rev. *D Page 5 of 12

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