NOP, STALL, and Deselect Cycles18, 19, Stall

CY7C1352G

NOP, STALL, and DESELECT Cycles[18, 19, 21]

BW[A:B]

CLK

tZZ

tZZI

ISUPPLY

I DDZZ

ALL INPUTS

(except ZZ)

tCHZ

NOP	READ	DESELECT CONTINUE
	Q(A5)	DESELECT

tZZREC

tRZZI

DESELECT or READ Only

Notes:

21.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

22.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

23.DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05514 Rev. *D

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Contents

Functional Description1 FeaturesLogic Block Diagram Cypress Semiconductor Corporation Selection Guide Pin ConfigurationMaximum Access Time Maximum Operating Current 250 MHz 200 MHz 166 MHz 133 MHz Unit Pin Definitions Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Truth Table for Read/Write 2 Ambient Range Maximum RatingsOperating Range GND ≤ V I ≤ V DDQ Thermal Resistance11 Capacitance11AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 16 Switching Waveforms Read/Write Timing18, 19 Stall ZZ Mode Timing22NOP, STALL, and Deselect Cycles18, 19 NOP Read Ordering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm Issue Orig. Description of Change Date Document History