32K x 8 3.3V Static RAMCY7C1399B
CypressSemiconductor Corporation • 3901North FirstStreet • SanJose • CA 95134 • 408-943-2600
Document #: 38-05071 Rev. *A Revised June 19, 2001
399B
Features
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
—10/12/15 ns
• Low active power
—216 mW (max.)
• Low-power alpha immune 6T cell
• Plastic SOJ and TSOP packaging
Functional Description
The CY7C1399B is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Ea sy me m ory ex -
pansion is provided by an active LOW Chip Enable (CE) and
active LOW Output Enable (OE) and three-state drivers. The
device has an automatic power-down feature, re ducing the
power consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by sel ecting the d evice
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/ output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399B is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
Logic Block Diagram Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O0
CE
I/O1
I/O2
I/O3
32Kx 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A9
A0
A
11
A
13
A
12
A
14
A
10