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Cypress CY7C1462AV25, CY7C1464AV25 manual 5V TAP AC Test Conditions, 8V TAP AC Test Conditions

Models: CY7C1462AV25 CY7C1460AV25 CY7C1464AV25

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

2.5V TAP AC Test Conditions

Input pulse levels	VSS to 2.5V
Input rise and fall time	1 ns
Input timing reference levels	1.25V
Output reference levels	1.25V
Test load termination supply voltage	1.25V

1.8V TAP AC Test Conditions

Input pulse levels	0.2V to VDDQ – 0.2
Input rise and fall time	1 ns
Input timing reference levels	0.9V
Output reference levels	0.9V
Test load termination supply voltage	0.9V

2.5V TAP AC Output Load Equivalent

1.8V TAP AC Output Load Equivalent

1.25V

0.9V

50Ω

50Ω

TDO

TDO

ZO= 50Ω

20pF

ZO= 50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; V = 2.5V ±0.125V unless otherwise noted)[11]

DD

Parameter

Description

Test Conditions

Min.

Max.

Unit

VOH1

Output HIGH Voltage

IOH = –1.0 mA

VDDQ = 2.5V

1.7

V

VOH2

Output HIGH Voltage

IOH = –100 ∝A

VDDQ = 2.5V

2.1

V

VDDQ = 1.8V

1.6

V

VOL1

Output LOW Voltage

IOL = 1.0 mA

VDDQ = 2.5V

0.4

V

VOL2

Output LOW Voltage

IOL = 100 ∝A

VDDQ = 2.5V

0.2

V

VDDQ = 1.8V

0.2

V

VIH

Input HIGH Voltage

VDDQ = 2.5V

1.7

VDD + 0.3

V

VDDQ = 1.8V

1.26

VDD + 0.3

V

VIL

Input LOW Voltage

VDDQ = 2.5V

–0.3

0.7

V

VDDQ = 1.8V

–0.3

0.36

V

IX

Input Load Current

GND ≤ VI ≤ VDDQ

–5

5

∝A

Identification Register Definitions

Instruction Field

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Description

(1M ×36)

(2M ×18)

(512K ×72)

Revision Number (31:29)

000

000

000

Describes the version number

Device Depth (28:24)

01011

01011

01011

Reserved for Internal Use

Architecture/Memory Type(23:18)

001000

001000

001000

Defines memory type and archi-

tecture

Bus Width/Density(17:12)

100111

010111

110111

Defines width and density

Cypress JEDEC ID Code (11:1)

00000110100

00000110100

00000110100

Allows unique identification of

SRAM vendor

ID Register Presence Indicator (0)

1

1

1

Indicates the presence of an ID

register

Note:

11. All voltages referenced to VSS (GND).

Document #: 38-05354 Rev. *D

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Cypress CY7C1462AV25 manual 5V TAP AC Test Conditions, 8V TAP AC Test Conditions, Identification Register Definitions

CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 specifications

The Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 are a family of high-performance synchronous SRAM devices that have been designed for applications requiring fast memory access and low latency. These memory chips are particularly appealing for systems in telecommunications, networking, and embedded applications due to their versatility and robust performance specifications.

One of the standout features of the CY7C1464AV25 series is their large capacities. The CY7C1464AV25 offers a capacity of 4 Megabits (512 K x 8), making it well-suited for applications that demand ample memory while maintaining high-speed operations. In contrast, the CY7C1460AV25 and CY7C1462AV25 provide slightly smaller capacities of 1 Megabit (128 K x 8) and 2 Megabits (256 K x 8) respectively, catering to varying system memory requirements.

All three devices utilize Cypress's advanced synchronous SRAM technology. This enables the chips to support burst read and write modes, allowing for rapid data transfer rates. The CY7C1464AV25 delivers a data access time of as low as 5.5 ns, making it highly efficient for data-intensive applications. Additionally, the standard operating voltage of 2.5V aids in reducing power consumption and improving overall system energy efficiency.

The chips are also characterized by a simple interface and compatibility with common bus protocols, which facilitates easy integration into existing systems. They feature a dual-port architecture, allowing multiple data transfers to occur simultaneously, significantly improving throughput.

With a commercial temperature range, all three devices offer reliability and are suited for a wide range of operating environments. The package options include a compact 44-pin TSOP, allowing for space-saving designs in modern electronics.

In summary, the Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 provide a powerful blend of capacity, speed, and efficiency, making them ideal choices for demanding applications in various sectors. Their advanced technologies and versatility make them excellent candidates for enhancing system performance while maintaining low power consumption and ensuring reliable operation in various conditions.

Contents

Logic Block Diagram-CY7C1460AV25 1M x FeaturesFunctional Description Cypress Semiconductor Corporation Logic Block Diagram-CY7C1464AV25 512K x Logic Block Diagram-CY7C1462AV25 2M xSelection Guide 250 MHz 200 MHz 167 MHz Unit 2M × Pin Configurations Pin Tqfp Pinout CY7C1462AV25 2M × Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with ADV/LD Power supply for the I/O circuitry Power supply inputs to the core of the deviceType Pin Description Clock input to the Jtag circuitry Burst Read Accesses Single Read AccessesSingle Write Accesses Burst Write Accesses Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Function CY7C1460AV25 BW d BW c BW b BW a Partial Write Cycle Description1, 2, 3Function CY7C1462AV25 Function CY7C1464AV25 Disabling the Jtag Feature TAP Controller Block Diagram TAP Controller State DiagramTest Access Port TAP Performing a TAP Reset TAP Instruction Set Bypass Register Parameter Description Min Max Unit Clock TAP TimingOutput Times Set-up Times 5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions8V TAP AC Test Conditions Identification Register Definitions Identification Codes Scan Register SizesRegister Name Bit Size Instruction Code Description CY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball ID Ball Fbga Boundary Scan Order12Bit# Ball ID CY7C1464AV25 512K x Bit# Ball ID Ball Fbga Boundary Scan Order 12 Maximum Ratings Electrical Characteristics Over the Operating Range14Operating Range Ambient Range Thermal Resistance Capacitance16AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 21 Read/Write/Timing23, 24 Switching WaveformsNOP, Stall and Deselect Cycles23, 24 DON’T Care ZZ Mode Timing27 Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package Diagrams Ball Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeSYT RXU