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Cypress CY7C1460AV25, CY7C1464AV25 manual Pin Definitions, Pin Name Type Pin Description, Adv/Ld

Models: CY7C1462AV25 CY7C1460AV25 CY7C1464AV25

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Pin Configurations (continued)

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1464AV25 (512K x 72)

1

2

3

4

5

6

7

8

9

10

11

A

DQg

DQg

A

CE2

3

A

DQb

A

ADV/LD

A

CE

DQb

B

DQg

DQg

A

BWSb

DQb

BWSc

BWSg

NC

WE

BWSf

DQb

C

DQg

DQg

NC/576M

1

NC

DQb

BWS

h

BWS

d

CE

BWS

e

BWS

a

DQb

D

DQg

DQg

VSS

NC/1G

NC

NC

VSS

NC

OE

DQb

DQb

E

DQPg

DQPc

VDDQ

VDDQ

VDD

VDD

VDD

VDDQ

VDDQ

DQPf

DQPb

F

DQc

DQc

VSS

VSS

VSS

NC

VSS

VSS

VSS

DQf

DQf

G

DQc

DQc

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQf

DQf

H

DQc

DQc

VSS

VSS

VSS

NC

VSS

VSS

VSS

DQf

DQf

J

DQc

DQc

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQf

DQf

K

NC

NC

CLK

NC

VSS

VSS

CEN

NC

NC

NC

NC

L

DQh

DQh

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQa

DQa

M

DQh

DQh

VSS

VSS

VSS

NC

VSS

VSS

VSS

DQa

DQa

N

DQh

DQh

VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQa

DQa

P

DQh

DQh

VSS

VSS

VSS

ZZ

VSS

VSS

VSS

DQa

DQa

R

DQPd

DQPh

VDDQ

VDDQ

VDD

VDD

VDD

VDDQ

VDDQ

DQPa

DQPe

T

DQd

DQd

VSS

NC

NC

MODE

NC

NC

VSS

DQe

DQe

U

DQd

DQd

NC/144M

A

NC/72M

A

A

A

NC/288M

DQe

DQe

V

DQd

DQd

A

A

A

A1

A

A

A

DQe

DQe

W

DQd

DQd

TMS

TDI

A

A0

A

TDO

TCK

DQe

DQe

Pin Definitions

Pin Name

I/O Type

Pin Description

A0

Input-

Address Inputs used to select one of the address locations. Sampled at the rising edge of

A1

Synchronous

the CLK.

A

a

Input-

Byte Write Select Inputs, active LOW. Qualified with

to conduct writes to the SRAM.

BW

WE

BWb

Synchronous

Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,

BWc

BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf

BWd

controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.

BWe

BWf

BWg

BWh

Input-

Write Enable Input, active LOW. Sampled on the rising edge of CLK if

is active LOW. This

WE

CEN

Synchronous

signal must be asserted LOW to initiate a write sequence.

Input-

Advance/Load Input used to advance the on-chip address counter or load a new address.

ADV/LD

Synchronous

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with

CEN.

Clock

CLK is only recognized if CEN is active LOW.

Document #: 38-05354 Rev. *D

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Cypress CY7C1460AV25 Pin Definitions, Pin Name Type Pin Description, Byte Write Select Inputs, active LOW. Qualified with

CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 specifications

The Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 are a family of high-performance synchronous SRAM devices that have been designed for applications requiring fast memory access and low latency. These memory chips are particularly appealing for systems in telecommunications, networking, and embedded applications due to their versatility and robust performance specifications.

One of the standout features of the CY7C1464AV25 series is their large capacities. The CY7C1464AV25 offers a capacity of 4 Megabits (512 K x 8), making it well-suited for applications that demand ample memory while maintaining high-speed operations. In contrast, the CY7C1460AV25 and CY7C1462AV25 provide slightly smaller capacities of 1 Megabit (128 K x 8) and 2 Megabits (256 K x 8) respectively, catering to varying system memory requirements.

All three devices utilize Cypress's advanced synchronous SRAM technology. This enables the chips to support burst read and write modes, allowing for rapid data transfer rates. The CY7C1464AV25 delivers a data access time of as low as 5.5 ns, making it highly efficient for data-intensive applications. Additionally, the standard operating voltage of 2.5V aids in reducing power consumption and improving overall system energy efficiency.

The chips are also characterized by a simple interface and compatibility with common bus protocols, which facilitates easy integration into existing systems. They feature a dual-port architecture, allowing multiple data transfers to occur simultaneously, significantly improving throughput.

With a commercial temperature range, all three devices offer reliability and are suited for a wide range of operating environments. The package options include a compact 44-pin TSOP, allowing for space-saving designs in modern electronics.

In summary, the Cypress CY7C1464AV25, CY7C1460AV25, and CY7C1462AV25 provide a powerful blend of capacity, speed, and efficiency, making them ideal choices for demanding applications in various sectors. Their advanced technologies and versatility make them excellent candidates for enhancing system performance while maintaining low power consumption and ensuring reliable operation in various conditions.

Contents

Logic Block Diagram-CY7C1460AV25 1M x FeaturesFunctional Description Cypress Semiconductor Corporation Logic Block Diagram-CY7C1464AV25 512K x Logic Block Diagram-CY7C1462AV25 2M xSelection Guide 250 MHz 200 MHz 167 MHz Unit 2M × Pin Configurations Pin Tqfp Pinout CY7C1462AV25 2M × Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with ADV/LD Power supply for the I/O circuitry Power supply inputs to the core of the deviceType Pin Description Clock input to the Jtag circuitry Burst Read Accesses Single Read AccessesSingle Write Accesses Burst Write Accesses ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Function CY7C1460AV25 BW d BW c BW b BW a Partial Write Cycle Description1, 2, 3Function CY7C1462AV25 Function CY7C1464AV25 Disabling the Jtag Feature TAP Controller Block Diagram TAP Controller State DiagramTest Access Port TAP Performing a TAP Reset TAP Instruction Set Bypass Register Parameter Description Min Max Unit Clock TAP TimingOutput Times Set-up Times 5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions8V TAP AC Test Conditions Identification Register Definitions Identification Codes Scan Register SizesRegister Name Bit Size Instruction Code Description Bit# Ball ID Ball Fbga Boundary Scan Order12CY7C1460AV25 1M x 36, CY7C1462AV25 2M x Bit# Ball ID CY7C1464AV25 512K x Bit# Ball ID Ball Fbga Boundary Scan Order 12 Maximum Ratings Electrical Characteristics Over the Operating Range14Operating Range Ambient Range AC Test Loads and Waveforms Capacitance16Thermal Resistance 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 21 NOP, Stall and Deselect Cycles23, 24 Switching WaveformsRead/Write/Timing23, 24 DON’T Care ZZ Mode Timing27 Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package Diagrams Ball Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeSYT RXU